|
43 | 43 | #define HP(state) (PMU_MODE_HP_ ## state) |
44 | 44 | #define LP(state) (PMU_MODE_LP_ ## state) |
45 | 45 |
|
| 46 | +#define DCDC_STARTUP_TIME_US (950) |
46 | 47 |
|
47 | 48 | static bool s_pmu_sleep_regdma_backup_enabled; |
48 | 49 |
|
@@ -290,6 +291,24 @@ static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_con |
290 | 291 | pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias); |
291 | 292 | pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b); |
292 | 293 |
|
| 294 | +#if CONFIG_ESP_SLEEP_KEEP_DCDC_ALWAYS_ON |
| 295 | + if (dslp) |
| 296 | +#endif |
| 297 | + { |
| 298 | +/** |
| 299 | + DCDC_EN will be controlled by software to avoid DCDC working in a non-feedback state, which may |
| 300 | + cause input glitch voltage when waking up and switching to LDO. |
| 301 | + 1. Lightsleep: |
| 302 | + CONFIG_ESP_SLEEP_KEEP_DCDC_ALWAYS_ON = y: DCDC will not shutdown during sleep. |
| 303 | + CONFIG_ESP_SLEEP_KEEP_DCDC_ALWAYS_ON = n: |
| 304 | + PD_TOP: DCDC_EN DCDC_EN enabled by regdma after wake up. |
| 305 | + PU_TOP: DCDC_EN DCDC_EN enabled by pmu_sleep_finish after wakeup. |
| 306 | + 2. Deepsleep |
| 307 | + After chip wake up from deepsleep, set DCDC_EN in rtc_clk_init. |
| 308 | +**/ |
| 309 | + pmu_ll_hp_set_dcm_mode(ctx->hal->dev, HP(ACTIVE), 0); |
| 310 | + } |
| 311 | + |
293 | 312 | pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.slp_dbias); |
294 | 313 | pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.dbias); |
295 | 314 | pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.drv_b); |
@@ -340,7 +359,7 @@ void pmu_sleep_increase_ldo_volt(void) { |
340 | 359 | } |
341 | 360 |
|
342 | 361 | void pmu_sleep_shutdown_dcdc(void) { |
343 | | - pmu_ll_set_dcdc_switch_force_power_down(&PMU, true); |
| 362 | + // Keep dcdc_switch on, will be disabled by PMU when entered sleep. |
344 | 363 | pmu_ll_set_dcdc_en(&PMU, false); |
345 | 364 | // Decrease hp_ldo voltage. |
346 | 365 | pmu_ll_hp_set_regulator_dbias(&PMU, PMU_MODE_HP_ACTIVE, HP_CALI_ACTIVE_DBIAS_DEFAULT); |
@@ -450,10 +469,12 @@ TCM_IRAM_ATTR bool pmu_sleep_finish(bool dslp) |
450 | 469 | { |
451 | 470 | pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, HP_CALI_ACTIVE_DCM_VSET_DEFAULT); |
452 | 471 | pmu_sleep_enable_dcdc(); |
453 | | - if (pmu_ll_hp_is_sleep_reject(&PMU)) { |
454 | | - // If sleep is rejected, the hardware wake-up process that turns on DCDC |
455 | | - // is skipped, and wait DCDC volt rise up by software here. |
456 | | - esp_rom_delay_us(950); |
| 472 | + if (pmu_ll_hp_is_sleep_reject(&PMU) || !s_pmu_sleep_regdma_backup_enabled) { |
| 473 | + // If sleep is rejected or regdma restore is skipped, the hardware wake-up process that |
| 474 | + // turns on DCDC is skipped, and wait DCDC volt rise up by software here. |
| 475 | + esp_rom_delay_us(DCDC_STARTUP_TIME_US); |
| 476 | + } else if (s_pmu_sleep_regdma_backup_enabled) { |
| 477 | + esp_rom_delay_us(DCDC_STARTUP_TIME_US - PMU_REGDMA_S2A_WORK_TIME_US); |
457 | 478 | } |
458 | 479 | pmu_sleep_shutdown_ldo(); |
459 | 480 | } |
|
0 commit comments