IDF 5.5-rc1

Jason2866 · web-flow · commit 7c1777007f42 · 2025-07-15T12:40:19.000+02:00
IDF 5.5-rc1
diff --git a/.gitlab/ci/common.yml b/.gitlab/ci/common.yml
@@ -40,7 +40,7 @@ variables:
   GIT_FETCH_EXTRA_FLAGS: "--no-recurse-submodules --prune --prune-tags"
   # we're using .cache folder for caches
   GIT_CLEAN_FLAGS: -ffdx -e .cache/
-  LATEST_GIT_TAG: v5.5-beta1
+  LATEST_GIT_TAG: v5.5-rc1
 
   SUBMODULE_FETCH_TOOL: "tools/ci/ci_fetch_submodule.py"
   # by default we will fetch all submodules
diff --git a/components/esp_hw_support/port/esp32c5/pmu_param.c b/components/esp_hw_support/port/esp32c5/pmu_param.c
@@ -439,7 +439,7 @@ uint32_t get_act_hp_dbias(void)
             hp_cali_dbias = 31;
         }
     } else {
-        ESP_HW_LOGW(TAG, "hp_cali_dbias not burnt in efuse, use default.");
+        ESP_HW_LOGD(TAG, "hp_cali_dbias not burnt in efuse, use default.");
     }
     return hp_cali_dbias;
 }
@@ -463,7 +463,7 @@ uint32_t get_act_lp_dbias(void)
             lp_cali_dbias = 31;
         }
     } else {
-        ESP_HW_LOGW(TAG, "hp_cali_dbias not burnt in efuse, use default.");
+        ESP_HW_LOGD(TAG, "lp_cali_dbias not burnt in efuse, use default.");
     }
 
     return lp_cali_dbias;
diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c
@@ -233,9 +233,21 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
     // 40MHz with PLL_F160M or PLL_F240M clock source. This is a special case, has to handle separately.
     if (xtal_freq == SOC_XTAL_FREQ_48M && freq_mhz == 40) {
         real_freq_mhz = freq_mhz;
-        source = SOC_CPU_CLK_SRC_PLL_F160M;
-        source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
-        divider = 4;
+        if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 101)) {
+#if CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240
+            source = SOC_CPU_CLK_SRC_PLL_F240M;
+            source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ;
+            divider = 6;
+#else
+            source = SOC_CPU_CLK_SRC_PLL_F160M;
+            source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
+            divider = 4;
+#endif
+        } else {
+            source = SOC_CPU_CLK_SRC_PLL_F160M;
+            source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
+            divider = 4;
+        }
     } else if (freq_mhz <= xtal_freq && freq_mhz != 0) {
         divider = xtal_freq / freq_mhz;
         real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
@@ -258,12 +270,18 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
         divider = 1;
     } else if (freq_mhz == 80) {
         real_freq_mhz = freq_mhz;
-        if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
+        if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 101)) {
             /* ESP32C5 has a root clock ICG issue when switching SOC_CPU_CLK_SRC from PLL_F160M to PLL_F240M
              * For detailed information, refer to IDF-11064 */
+#if CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240
             source = SOC_CPU_CLK_SRC_PLL_F240M;
             source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ;
             divider = 3;
+#else
+            source = SOC_CPU_CLK_SRC_PLL_F160M;
+            source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
+            divider = 2;
+#endif
         } else {
             source = SOC_CPU_CLK_SRC_PLL_F160M;
             source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ;
@@ -393,8 +411,22 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
 
 void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
 {
-    // TODO: IDF-8641 CPU_MAX_FREQ don't know what to do... pll_240 or pll_160...
-    rtc_clk_cpu_freq_to_pll_240_mhz(cpu_freq_mhz);
+    //                          IDF-11064
+    if (cpu_freq_mhz == 240) {
+        rtc_clk_cpu_freq_to_pll_240_mhz(cpu_freq_mhz);
+    } else if (cpu_freq_mhz == 160) {
+        rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz);
+    } else {// cpu_freq_mhz is 80
+        if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 101)) {// (use 240mhz pll if max cpu freq is 240MHz)
+#if CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240
+            rtc_clk_cpu_freq_to_pll_240_mhz(cpu_freq_mhz);
+#else
+            rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz);
+#endif
+        } else {// (fixed for chip rev. >= ECO3)
+            rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz);
+        }
+    }
     clk_ll_cpu_clk_src_lock_release();
 }
 
diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld
@@ -133,7 +133,7 @@ pm_rx_beacon_process = 0x40000dac;
 pm_rx_data_process = 0x40000db0;
 pm_sleep = 0x40000db4;
 pm_sleep_for = 0x40000db8;
-pm_tbtt_process = 0x40000dbc;
+//pm_tbtt_process = 0x40000dbc;
 pm_tx_data_done_process = 0x40000dc0;
 pm_allow_tx = 0x40000dc4;
 pm_extend_tbtt_adaptive_servo = 0x40000dc8;
@@ -151,9 +151,9 @@ pm_twt_set_target_tsf = 0x40000df4;
 pm_enable_twt_keep_alive_timer = 0x40000df8;
 /*pm_mac_try_enable_modem_state = 0x40000dfc;*/
 pm_beacon_monitor_tbtt_timeout_process = 0x40000e00;
-pm_update_next_tbtt = 0x40000e04;
+//pm_update_next_tbtt = 0x40000e04;
 pm_twt_disallow_tx = 0x40000e08;
-pm_clear_wakeup_signal = 0x40000e0c;
+//pm_clear_wakeup_signal = 0x40000e0c;
 //pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000e10;
 //pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000e14;
 //pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000e18;
@@ -462,9 +462,9 @@ pm_coex_schm_overall_period_get = 0x40001504;
 //pm_coex_pwr_update = 0x40001508;
 ppRemoveHEAMPDUflags = 0x4000150c;
 tsf_hal_get_tbtt_interval = 0x40001510;
-pm_beacon_monitor_tbtt_start = 0x40001514;
+//pm_beacon_monitor_tbtt_start = 0x40001514;
 pm_save_tbtt_info = 0x40001518;
-pm_get_tbtt_count = 0x4000151c;
+//pm_get_tbtt_count = 0x4000151c;
 tsf_hal_get_time = 0x40001520;
 tsf_hal_get_counter_value = 0x40001524;
 
@@ -488,10 +488,10 @@ pm_beacon_offset_is_enabled = 0x400015bc;
 pm_beacon_offset_is_sampling = 0x400015c0;
 pm_beacon_offset_add_total_counter = 0x400015c4;
 pm_beacon_offset_add_loss_counter = 0x400015c8;
-pm_beacon_offset_check = 0x400015cc;
-pm_beacon_offset_get_average = 0x400015d0;
-pm_beacon_offset_get_expect = 0x400015d4;
-pm_beacon_offset_get_params = 0x400015d8;
+//pm_beacon_offset_check = 0x400015cc;
+//pm_beacon_offset_get_average = 0x400015d0;
+//pm_beacon_offset_get_expect = 0x400015d4;
+//pm_beacon_offset_get_params = 0x400015d8;
 /* Data (.data, .bss, .rodata) */
 s_tbttstart_ptr = 0x4085fc68;
 s_pm_beacon_offset_ptr = 0x4085fc64;
diff --git a/components/esp_system/port/soc/esp32c5/system_internal.c b/components/esp_system/port/soc/esp32c5/system_internal.c
@@ -22,6 +22,7 @@
 #include "soc/rtc_periph.h"
 #include "soc/uart_reg.h"
 #include "hal/wdt_hal.h"
+#include "hal/uart_ll.h"
 #if SOC_MODEM_CLOCK_SUPPORTED
 #include "hal/modem_syscon_ll.h"
 #include "hal/modem_lpcon_ll.h"
@@ -82,6 +83,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
     SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+
+    // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
+    // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
+    uart_ll_sclk_enable(&UART0);
 }
 
 /* "inner" restart function for after RTOS, interrupts & anything else on this
diff --git a/components/esp_system/port/soc/esp32c6/system_internal.c b/components/esp_system/port/soc/esp32c6/system_internal.c
@@ -20,6 +20,7 @@
 #include "esp_private/rtc_clk.h"
 #include "soc/rtc_periph.h"
 #include "soc/uart_reg.h"
+#include "hal/uart_ll.h"
 #include "hal/wdt_hal.h"
 #include "hal/modem_syscon_ll.h"
 #include "hal/modem_lpcon_ll.h"
@@ -75,6 +76,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+
+    // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
+    // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
+    uart_ll_sclk_enable(&UART0);
 }
 
 /* "inner" restart function for after RTOS, interrupts & anything else on this
diff --git a/components/esp_system/port/soc/esp32c61/system_internal.c b/components/esp_system/port/soc/esp32c61/system_internal.c
@@ -20,6 +20,7 @@
 #include "esp_private/rtc_clk.h"
 #include "soc/rtc_periph.h"
 #include "soc/uart_reg.h"
+#include "hal/uart_ll.h"
 #include "hal/wdt_hal.h"
 #include "esp_private/cache_err_int.h"
 
@@ -82,6 +83,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
     SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+
+    // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
+    // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
+    uart_ll_sclk_enable(&UART0);
 }
 
 /* "inner" restart function for after RTOS, interrupts & anything else on this
diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c
@@ -23,6 +23,7 @@
 #include "soc/uart_reg.h"
 #include "hal/wdt_hal.h"
 #include "hal/spimem_flash_ll.h"
+#include "hal/uart_ll.h"
 #include "esp_private/cache_err_int.h"
 #include "esp_private/mspi_timing_tuning.h"
 
@@ -73,6 +74,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+
+    // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
+    // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
+    uart_ll_sclk_enable(&UART0);
 }
 
 /* "inner" restart function for after RTOS, interrupts & anything else on this
diff --git a/components/esp_system/port/soc/esp32h21/system_internal.c b/components/esp_system/port/soc/esp32h21/system_internal.c
@@ -20,6 +20,7 @@
 #include "esp_private/rtc_clk.h"
 #include "soc/rtc_periph.h"
 #include "soc/uart_reg.h"
+#include "hal/uart_ll.h"
 #include "hal/wdt_hal.h"
 #include "hal/spimem_flash_ll.h"
 #include "esp_private/cache_err_int.h"
@@ -77,6 +78,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_RSA_CONF_REG, PCR_RSA_RST_EN);
     SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+
+    // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
+    // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
+    uart_ll_sclk_enable(&UART0);
 }
 
 /* "inner" restart function for after RTOS, interrupts & anything else on this
diff --git a/components/esp_system/port/soc/esp32h4/system_internal.c b/components/esp_system/port/soc/esp32h4/system_internal.c
@@ -20,6 +20,7 @@
 #include "soc/rtc_periph.h"
 #include "soc/uart_reg.h"
 #include "hal/wdt_hal.h"
+#include "hal/uart_ll.h"
 
 #include "esp32h4/rom/cache.h"
 // TODO: IDF-11911 need refactor
@@ -69,6 +70,10 @@ void IRAM_ATTR esp_system_reset_modules_on_exit(void)
     CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
     SET_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
     CLEAR_PERI_REG_MASK(PCR_SHA_CONF_REG, PCR_SHA_RST_EN);
+
+    // UART's sclk is controlled in the PCR register and does not reset with the UART module. The ROM missed enabling
+    // it when initializing the ROM UART. If it is not turned on, it will trigger LP_WDT in the ROM.
+    uart_ll_sclk_enable(&UART0);
 }
 
 /* "inner" restart function for after RTOS, interrupts & anything else on this
diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib
@@ -1 +1 @@
-Subproject commit 561f3904efa6fa3ac9fa6213985c118bcb9ed800
+Subproject commit 61cdea8dbcb1cd409cb7ec2bc0913c3b17eea911
diff --git a/components/wpa_supplicant/esp_supplicant/src/esp_eap_client.c b/components/wpa_supplicant/esp_supplicant/src/esp_eap_client.c
@@ -60,6 +60,7 @@ static struct eap_sm *gEapSm = NULL;
 
 static int eap_peer_sm_init(void);
 static void eap_peer_sm_deinit(void);
+static void eap_start_eapol(void *ctx, void *data);
 
 static int eap_sm_rx_eapol_internal(u8 *src_addr, u8 *buf, u32 len, uint8_t *bssid);
 static int wpa2_start_eapol_internal(void);
@@ -529,6 +530,10 @@ static int eap_sm_rx_eapol_internal(u8 *src_addr, u8 *buf, u32 len, uint8_t *bss
         return ESP_FAIL;
     }
 
+    if (!sm->eap_process_started) {
+        sm->eap_process_started = true;
+        eloop_cancel_timeout(eap_start_eapol, NULL, NULL);
+    }
     if (len < sizeof(*hdr) + sizeof(*ehdr)) {
         wpa_printf(MSG_DEBUG, "WPA: EAPOL frame too short to be a WPA "
                    "EAPOL-Key (len %lu, expecting at least %lu)",
@@ -612,15 +617,28 @@ static int eap_sm_rx_eapol_internal(u8 *src_addr, u8 *buf, u32 len, uint8_t *bss
     return ret;
 }
 
-static int wpa2_start_eapol(void)
+static void eap_start_eapol(void *ctx, void *data)
 {
 #ifdef USE_WPA2_TASK
-    return wpa2_post(SIG_WPA2_START, 0);
+    wpa2_post(SIG_WPA2_START, 0);
 #else
-    return wpa2_start_eapol_internal();
+    wpa2_start_eapol_internal();
 #endif
 }
 
+static int eap_start_eapol_timer(void)
+{
+    /*
+     * Do not send EAPOL-Start immediately since in most cases,
+     * Authenticator is going to start authentication immediately
+     * after association and an extra EAPOL-Start is just going to
+     * delay authentication. Use a short timeout to send the first
+     * EAPOL-Start if Authenticator does not start authentication.
+     */
+    eloop_register_timeout(2, 0, eap_start_eapol, NULL, NULL);
+    return 0;
+}
+
 static int wpa2_start_eapol_internal(void)
 {
     struct eap_sm *sm = gEapSm;
@@ -739,6 +757,7 @@ static int eap_peer_sm_init(void)
     wpa_printf(MSG_INFO, "wifi_task prio:%d, stack:%d", WPA2_TASK_PRIORITY, WPA2_TASK_STACK_SIZE);
 #endif
     sm->workaround = 1;
+    sm->eap_process_started = false;
     return ESP_OK;
 
 _err:
@@ -806,7 +825,7 @@ static esp_err_t esp_client_enable_fn(void *arg)
     }
 
     wpa2_cb->wpa2_sm_rx_eapol = wpa2_ent_rx_eapol;
-    wpa2_cb->wpa2_start = wpa2_start_eapol;
+    wpa2_cb->wpa2_start = eap_start_eapol_timer;
     wpa2_cb->wpa2_init = eap_peer_sm_init;
     wpa2_cb->wpa2_deinit = eap_peer_sm_deinit;
 
diff --git a/components/wpa_supplicant/src/eap_peer/eap_i.h b/components/wpa_supplicant/src/eap_peer/eap_i.h
@@ -311,6 +311,7 @@ struct eap_sm {
 	size_t eapKeyDataLen;
 	struct wpabuf *lastRespData;
 	const struct eap_method *m;
+	bool eap_process_started;
 };
 
 typedef enum {
diff --git a/examples/wifi/itwt/main/Kconfig.projbuild b/examples/wifi/itwt/main/Kconfig.projbuild
@@ -119,7 +119,7 @@ menu "Example Configuration"
             depends on !IDF_TARGET_ESP32C2
         config EXAMPLE_MAX_CPU_FREQ_240
             bool "240 MHz"
-            depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
+            depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C5
     endchoice
 
     config EXAMPLE_MAX_CPU_FREQ_MHZ
@@ -131,7 +131,8 @@ menu "Example Configuration"
 
     choice EXAMPLE_MIN_CPU_FREQ
         prompt "Minimum CPU frequency"
-        default EXAMPLE_MIN_CPU_FREQ_10M
+        default EXAMPLE_MIN_CPU_FREQ_10M if !IDF_TARGET_ESP32C5
+        default EXAMPLE_MIN_CPU_FREQ_12M if IDF_TARGET_ESP32C5
         depends on PM_ENABLE
         help
             Minimum CPU frequency to use for dynamic frequency scaling.
@@ -143,6 +144,9 @@ menu "Example Configuration"
         config EXAMPLE_MIN_CPU_FREQ_20M
             bool "20 MHz (use with 40MHz XTAL)"
             depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO
+        config EXAMPLE_MIN_CPU_FREQ_12M
+            bool "12 MHz (use with 48MHz XTAL)"
+            depends on XTAL_FREQ_48 || XTAL_FREQ_AUTO
         config EXAMPLE_MIN_CPU_FREQ_10M
             bool "10 MHz (use with 40MHz XTAL)"
             depends on XTAL_FREQ_40 || XTAL_FREQ_AUTO
@@ -161,5 +165,6 @@ menu "Example Configuration"
         default 10 if EXAMPLE_MIN_CPU_FREQ_10M
         default 26 if EXAMPLE_MIN_CPU_FREQ_26M
         default 13 if EXAMPLE_MIN_CPU_FREQ_13M
+        default 12 if EXAMPLE_MIN_CPU_FREQ_12M
 
 endmenu
diff --git a/examples/wifi/itwt/main/itwt_main.c b/examples/wifi/itwt/main/itwt_main.c

Original file line number	Diff line number	Diff line change
`@@ -439,7 +439,7 @@ uint32_t get_act_hp_dbias(void)`
`439`	`439`	`hp_cali_dbias = 31;`
`440`	`440`	`}`
`441`	`441`	`} else {`
`442`		`- ESP_HW_LOGW(TAG, "hp_cali_dbias not burnt in efuse, use default.");`
	`442`	`+ ESP_HW_LOGD(TAG, "hp_cali_dbias not burnt in efuse, use default.");`
`443`	`443`	`}`
`444`	`444`	`return hp_cali_dbias;`
`445`	`445`	`}`
`@@ -463,7 +463,7 @@ uint32_t get_act_lp_dbias(void)`
`463`	`463`	`lp_cali_dbias = 31;`
`464`	`464`	`}`
`465`	`465`	`} else {`
`466`		`- ESP_HW_LOGW(TAG, "hp_cali_dbias not burnt in efuse, use default.");`
	`466`	`+ ESP_HW_LOGD(TAG, "lp_cali_dbias not burnt in efuse, use default.");`
`467`	`467`	`}`
`468`	`468`
`469`	`469`	`return lp_cali_dbias;`