Merge branch 'fix/p4_rev3_further_fixes_v5.5' into 'release/v5.5'

fix(esp_hw_support): p4 rev3 further fixes  (v5.5)

See merge request espressif/esp-idf!42942

Author: Jiang Jiang Jian

components/bootloader_support/src/bootloader_common_loader.c

@@ -263,7 +263,11 @@ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void)
 #ifdef BOOTLOADER_BUILD
 
 #if ESP_ROM_HAS_LP_ROM
+#if CONFIG_IDF_TARGET_ESP32P4
+    #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_LOW + CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE)
+#else
     #define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_LOW)
+#endif
 #else
     /* Since the structure containing the retain_mem_t is aligned on 8 by the linker, make sure we align this
      * structure size here too */

components/esp_hw_support/CMakeLists.txt

@@ -56,6 +56,7 @@ if(NOT non_os_build)
         list(APPEND srcs "sleep_modem.c"
                          "sleep_modes.c"
                          "sleep_console.c"
+                         "sleep_mspi.c"
                          "sleep_usb.c"
                          "sleep_gpio.c"
                          "sleep_event.c"

components/esp_hw_support/Kconfig

@@ -309,4 +309,5 @@ menu "Hardware Settings"
         bool "Place esp_intr_alloc functions in IRAM" if SPI_FLASH_AUTO_SUSPEND
         default y
 
+    orsource "./lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround"
 endmenu

components/esp_hw_support/include/esp_private/esp_pmu.h

@@ -346,11 +346,6 @@ void pmu_init(void);
  */
 uint32_t pmu_sleep_get_wakup_retention_cost(void);
 
-/**
- * Workaround for esp32p4 v3 MPSI access failure after power up.
- */
-void pmu_sleep_p4_rev3_workaround(void);
-
 #endif //#if SOC_PMU_SUPPORTED
 
 #ifdef __cplusplus

components/esp_hw_support/include/esp_private/sleep_flash.h

@@ -0,0 +1,25 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "soc/soc_caps.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if CONFIG_IDF_TARGET_ESP32P4 && (CONFIG_ESP_REV_MIN_FULL == 300)
+/**
+ * Workaround for esp32p4 v3 MPSI access failure after power up.
+ */
+void sleep_flash_p4_rev3_workaround(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/linker.lf

@@ -35,6 +35,7 @@ entries:
         rtc_sleep:rtc_sleep_pu (noflash)
     if SOC_PMU_SUPPORTED = y && SOC_LIGHT_SLEEP_SUPPORTED = y:
         pmu_sleep (noflash)
+        sleep_mspi (noflash)
         if SPIRAM_FLASH_LOAD_TO_PSRAM = y:
             pmu_init (noflash)
             pmu_param (noflash)

components/esp_hw_support/lowpower/CMakeLists.txt

@@ -18,6 +18,12 @@ if(CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP OR
     endif()
 endif()
 
+if(CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND)
+    list(APPEND srcs "port/esp32p4/p4_rev3_mspi_workaround.S")
+    set_property(TARGET ${COMPONENT_LIB}
+                APPEND PROPERTY INTERFACE_LINK_LIBRARIES "-u p4_rev3_mspi_workaround")
+endif()
+
 if(CONFIG_SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD AND CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP)
     list(APPEND srcs "port/${target}/sleep_mmu.c")
 endif()

components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround

@@ -0,0 +1,10 @@
+config P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
+    bool
+    depends on IDF_TARGET_ESP32P4
+    default y if ESP32P4_REV_MIN_300
+
+config P4_REV3_MSPI_WORKAROUND_SIZE
+    hex
+    depends on IDF_TARGET_ESP32P4
+    default 0x100 if ESP32P4_REV_MIN_300
+    default 0

components/esp_hw_support/lowpower/port/esp32p4/p4_rev3_mspi_workaround.S

@@ -0,0 +1,110 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/reg_base.h"
+
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_REG     (DR_REG_HP_SYS_BASE + 0x1a4)
+
+/* Clock related */
+#define DR_REG_LP_CLKRST_BASE               (DR_REG_LPAON_BASE + 0x1000)
+#define LP_CLKRST_HPCPU_RESET_CTRL0_REG     (DR_REG_LP_CLKRST_BASE + 0x14)
+#define LP_CLKRST_HPCORE0_STAT_VECTOR_SEL   (1 << 15)
+
+#define HP_SYS_CLKRST_HP_RST_EN0_REG        (DR_REG_HP_SYS_CLKRST_BASE + 0xc0)
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI    (1 << 22)
+#define HP_SYS_CLKRST_REG_RST_EN_MSPI_APB    (1 << 24)
+
+
+/* SPIMEM related */
+#define DR_REG_FLASH_SPI0_BASE              (DR_REG_HPPERIPH0_BASE + 0x8C000)
+#define SPI_MEM_C_CACHE_FCTRL_REG           (DR_REG_FLASH_SPI0_BASE + 0x3c)
+#define SPI_MEM_C_CLOSE_AXI_INF_EN          (1 << 31)
+#define SPI_MEM_C_AXI_REQ_EN                (1 << 0)
+
+#define SPI_MEM_C_MMU_ITEM_INDEX_REG        (DR_REG_FLASH_SPI0_BASE + 0x380)
+#define SPI_MEM_C_MMU_ITEM_CONTENT_REG      (DR_REG_FLASH_SPI0_BASE + 0x37c)
+
+.macro REG_SET_BIT addr, value
+    li a0, \addr
+    li a1, \value
+    lw a2, (a0)
+    or a2, a2, a1
+    sw a2, (a0)
+.endm
+
+.macro REG_CLR_BIT addr, value
+    li a0, \addr
+    /* Since all our parameters will be constants, we can pre-calculate it at assemble time */
+    li a1, ~\value
+    lw a2, (a0)
+    and a2, a2, a1
+    sw a2, (a0)
+.endm
+
+.macro REG_WRITE addr, value
+    li a0, \addr
+    li a1, \value
+    sw a1, (a0)
+.endm
+
+.macro REG_READ addr
+    li  a0, \addr
+    lw  a1, (a0)
+.endm
+
+.macro DELAY_US us
+    li      t3, (40 * \us)     /* CPU @40MHz after reset */
+    csrr    t0, cycle
+    add     t1, t0, t3
+1:  csrr    t2, cycle
+    blt     t2, t1, 1b
+.endm
+
+/**
+ * @brief Workaround for MSPI issues on ESP32-P4 revision 3
+ *
+ * This function implements a workaround for MSPI-related issues on ESP32-P4 revision 3.
+ * It performs 2 flash dummy reads to stabilize the MSPI functionality before jumping to
+ * ROM code after deepsleep wakeup.
+ */
+.global p4_rev3_mspi_workaround
+.section .p4_rev3_mspi_workaround.rtc_text,"ax"
+
+p4_rev3_mspi_workaround:
+    # Recover the reset vector to HP ROM
+    REG_SET_BIT LP_CLKRST_HPCPU_RESET_CTRL0_REG, LP_CLKRST_HPCORE0_STAT_VECTOR_SEL
+
+    # Clear the bit to close AXI interface and then set the AXI request enable bit
+    REG_CLR_BIT SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_CLOSE_AXI_INF_EN
+    REG_SET_BIT SPI_MEM_C_CACHE_FCTRL_REG, SPI_MEM_C_AXI_REQ_EN
+
+    # Set 1 mspi mmu entry for axi addr to flash addr
+    REG_WRITE SPI_MEM_C_MMU_ITEM_INDEX_REG, 0
+    REG_WRITE SPI_MEM_C_MMU_ITEM_CONTENT_REG, 0x1000
+
+    # Disable cpu get error response
+    REG_WRITE HP_SYSTEM_CORE_ERR_RESP_DIS_REG, 0x7
+
+    # Perform dummy reads
+    REG_READ 0x80000000
+    # Perform dummy reads again
+    REG_READ 0x80000080
+
+    # Delay 1us to wait MSPI read transmission done
+    DELAY_US 1
+
+    # Enable cpu get error response
+    REG_WRITE HP_SYSTEM_CORE_ERR_RESP_DIS_REG, 0
+
+    # Reset MSPI AXI and APB interfaces
+    REG_SET_BIT HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI
+    REG_SET_BIT HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_APB
+    REG_CLR_BIT HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI
+    REG_CLR_BIT HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_APB
+
+    # Jump to HP ROM first stage boot code
+    li  a5, 0x4fc00000
+    jr  a5

components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c

@@ -402,7 +402,11 @@ static TCM_IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
         }
 #endif
 
-        return (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp);
+        uint32_t reject =  (*goto_sleep)(wakeup_opt, reject_opt, lslp_mem_inf_fpu, dslp);
+        if (reject) {
+            restore_mstatus(mstatus);
+            return reject;
+        }
     }
 #if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
     else {