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1 parent d5ff5d3 commit a441cadCopy full SHA for a441cad
components/esp_hw_support/port/esp32c5/rtc_clk.c
@@ -411,8 +411,12 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
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void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
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{
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- // TODO: IDF-8641 CPU_MAX_FREQ don't know what to do... pll_240 or pll_160...
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- rtc_clk_cpu_freq_to_pll_240_mhz(cpu_freq_mhz);
+ // IDF-11064
+ if (cpu_freq_mhz == 240 || (cpu_freq_mhz == 80 && !ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1))) {
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+ rtc_clk_cpu_freq_to_pll_240_mhz(cpu_freq_mhz);
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+ } else { // cpu_freq_mhz is 160 or 80 (fixed for chip rev. >= ECO1)
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+ rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz);
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+ }
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clk_ll_cpu_clk_src_lock_release();
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}
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