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mythbuster5mythbuster5
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refactor(spi_flash): Refactor gpspi flash for making it's clock accurate
1 parent 018d7c5 commit ff1c10e

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25 files changed

+552
-19
lines changed

25 files changed

+552
-19
lines changed

‎components/hal/esp32c2/include/hal/gpspi_flash_ll.h‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -425,6 +425,35 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
425425
return div_parameter;
426426
}
427427

428+
/**
429+
* Set the clock source
430+
*
431+
* @param hw Beginning address of the peripheral registers.
432+
* @param clk_source Clock source to use
433+
*/
434+
static inline void gpspi_flash_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
435+
{
436+
switch (clk_source) {
437+
case SPI_CLK_SRC_XTAL:
438+
hw->clk_gate.mst_clk_sel = 0;
439+
break;
440+
default:
441+
hw->clk_gate.mst_clk_sel = 1;
442+
break;
443+
}
444+
}
445+
446+
/**
447+
* Enable/disable SPI flash module clock
448+
*
449+
* @param hw Beginning address of the peripheral registers.
450+
* @param enable true to enable, false to disable
451+
*/
452+
static inline void gpspi_flash_ll_enable_clock(spi_dev_t *hw, bool enable)
453+
{
454+
hw->clk_gate.clk_en = enable;
455+
}
456+
428457
#ifdef __cplusplus
429458
}
430459
#endif

‎components/hal/esp32c2/include/hal/spi_flash_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ extern "C" {
2424
#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
2525
: gpspi_flash_ll_calculate_clock_reg(clock_div))
2626

27-
#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ)
27+
#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : -1)
2828

2929
#define spi_flash_ll_get_hw(host_id) (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \
3030
: gpspi_flash_ll_get_hw(host_id)))

‎components/hal/esp32c3/include/hal/gpspi_flash_ll.h‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -426,6 +426,35 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
426426
return div_parameter;
427427
}
428428

429+
/**
430+
* Set the clock source
431+
*
432+
* @param hw Beginning address of the peripheral registers.
433+
* @param clk_source Clock source to use
434+
*/
435+
static inline void gpspi_flash_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
436+
{
437+
switch (clk_source) {
438+
case SPI_CLK_SRC_XTAL:
439+
hw->clk_gate.mst_clk_sel = 0;
440+
break;
441+
default:
442+
hw->clk_gate.mst_clk_sel = 1;
443+
break;
444+
}
445+
}
446+
447+
/**
448+
* Enable/disable SPI flash module clock
449+
*
450+
* @param hw Beginning address of the peripheral registers.
451+
* @param enable true to enable, false to disable
452+
*/
453+
static inline void gpspi_flash_ll_enable_clock(spi_dev_t *hw, bool enable)
454+
{
455+
hw->clk_gate.clk_en = enable;
456+
}
457+
429458
#ifdef __cplusplus
430459
}
431460
#endif

‎components/hal/esp32c3/include/hal/spi_flash_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ extern "C" {
2424
#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
2525
: gpspi_flash_ll_calculate_clock_reg(clock_div))
2626

27-
#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ)
27+
#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : -1)
2828

2929
#define spi_flash_ll_get_hw(host_id) (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \
3030
: gpspi_flash_ll_get_hw(host_id)))

‎components/hal/esp32c5/include/hal/gpspi_flash_ll.h‎

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,8 @@
1515
#include <stdlib.h>
1616
#include "soc/spi_periph.h"
1717
#include "soc/spi_struct.h"
18+
#include "soc/pcr_struct.h"
19+
#include "hal/assert.h"
1820
#include "hal/spi_types.h"
1921
#include "hal/spi_flash_types.h"
2022
#include <sys/param.h> // For MIN/MAX
@@ -31,6 +33,8 @@ extern "C" {
3133

3234
typedef typeof(GPSPI2.clock.val) gpspi_flash_ll_clock_reg_t;
3335
#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ (80)
36+
#define GPSPI_FLASH_LL_SUPPORT_CLK_SRC_PRE_DIV (1)
37+
#define GPSPI_FLASH_LL_PERIPH_CLK_DIV_MAX ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider
3438

3539
/*------------------------------------------------------------------------------
3640
* Control
@@ -426,6 +430,56 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
426430
return div_parameter;
427431
}
428432

433+
/**
434+
* Set the clock source
435+
*
436+
* @param hw Beginning address of the peripheral registers.
437+
* @param clk_source Clock source to use
438+
*/
439+
static inline void gpspi_flash_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
440+
{
441+
uint32_t clk_id = 0;
442+
switch (clk_source) {
443+
case SOC_MOD_CLK_PLL_F160M:
444+
clk_id = 1;
445+
break;
446+
case SOC_MOD_CLK_RC_FAST:
447+
clk_id = 2;
448+
break;
449+
case SOC_MOD_CLK_XTAL:
450+
clk_id = 0;
451+
break;
452+
default:
453+
HAL_ASSERT(false);
454+
}
455+
456+
PCR.spi2_clkm_conf.spi2_clkm_sel = clk_id;
457+
}
458+
459+
/**
460+
* Enable/disable SPI flash module clock
461+
*
462+
* @param host_id SPI host ID
463+
* @param enable true to enable, false to disable
464+
*/
465+
static inline void gpspi_flash_ll_enable_clock(spi_dev_t *hw, bool enable)
466+
{
467+
PCR.spi2_clkm_conf.spi2_clkm_en = enable;
468+
}
469+
470+
/**
471+
* Enable/disable SPI flash module clock
472+
*
473+
* @param hw Beginning address of the peripheral registers.
474+
* @param enable true to enable, false to disable
475+
*/
476+
static inline void gpspi_flash_ll_clk_source_pre_div(spi_dev_t *hw, uint8_t hs_div, uint8_t mst_div)
477+
{
478+
// In IDF master driver 'mst_div' will be const 2 and 'hs_div' is actually pre_div temporally
479+
(void) hs_div;
480+
HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.spi2_clkm_conf, spi2_clkm_div_num, mst_div - 1);
481+
}
482+
429483
#ifdef __cplusplus
430484
}
431485
#endif

‎components/hal/esp32c5/include/hal/spi_flash_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ extern "C" {
2626
#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
2727
: gpspi_flash_ll_calculate_clock_reg(clock_div))
2828

29-
#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ)
29+
#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : -1)
3030

3131
#define spi_flash_ll_get_hw(host_id) (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \
3232
: gpspi_flash_ll_get_hw(host_id)))

‎components/hal/esp32c6/include/hal/gpspi_flash_ll.h‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include <stdlib.h>
1616
#include "soc/spi_periph.h"
1717
#include "soc/spi_struct.h"
18+
#include "soc/pcr_struct.h"
1819
#include "hal/spi_types.h"
1920
#include "hal/spi_flash_types.h"
2021
#include <sys/param.h> // For MIN/MAX
@@ -426,6 +427,39 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
426427
return div_parameter;
427428
}
428429

430+
/**
431+
* Set the clock source
432+
*
433+
* @param hw Beginning address of the peripheral registers.
434+
* @param clk_source Clock source to use
435+
*/
436+
static inline void gpspi_flash_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
437+
{
438+
switch (clk_source) {
439+
case SPI_CLK_SRC_RC_FAST:
440+
PCR.spi2_clkm_conf.spi2_clkm_sel = 2;
441+
break;
442+
case SPI_CLK_SRC_XTAL:
443+
PCR.spi2_clkm_conf.spi2_clkm_sel = 0;
444+
break;
445+
default:
446+
PCR.spi2_clkm_conf.spi2_clkm_sel = 1;
447+
break;
448+
}
449+
}
450+
451+
/**
452+
* Enable/disable SPI flash module clock
453+
*
454+
* @param hw Beginning address of the peripheral registers.
455+
* @param enable true to enable, false to disable
456+
*/
457+
static inline void gpspi_flash_ll_enable_clock(spi_dev_t *hw, bool enable)
458+
{
459+
(void) hw;
460+
PCR.spi2_clkm_conf.spi2_clkm_en = enable;
461+
}
462+
429463
#ifdef __cplusplus
430464
}
431465
#endif

‎components/hal/esp32c6/include/hal/spi_flash_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ extern "C" {
2424
#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
2525
: gpspi_flash_ll_calculate_clock_reg(clock_div))
2626

27-
#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ)
27+
#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : -1)
2828

2929
#define spi_flash_ll_get_hw(host_id) (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \
3030
: gpspi_flash_ll_get_hw(host_id)))

‎components/hal/esp32c61/include/hal/gpspi_flash_ll.h‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include <stdlib.h>
1616
#include "soc/spi_periph.h"
1717
#include "soc/spi_struct.h"
18+
#include "soc/pcr_struct.h"
1819
#include "hal/spi_types.h"
1920
#include "hal/spi_flash_types.h"
2021
#include <sys/param.h> // For MIN/MAX
@@ -426,6 +427,39 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
426427
return div_parameter;
427428
}
428429

430+
/**
431+
* Set the clock source
432+
*
433+
* @param hw Beginning address of the peripheral registers.
434+
* @param clk_source Clock source to use
435+
*/
436+
static inline void gpspi_flash_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
437+
{
438+
switch (clk_source) {
439+
case SPI_CLK_SRC_RC_FAST:
440+
PCR.spi2_clkm_conf.spi2_clkm_sel = 2;
441+
break;
442+
case SPI_CLK_SRC_XTAL:
443+
PCR.spi2_clkm_conf.spi2_clkm_sel = 0;
444+
break;
445+
default:
446+
PCR.spi2_clkm_conf.spi2_clkm_sel = 1;
447+
break;
448+
}
449+
}
450+
451+
/**
452+
* Enable/disable SPI flash module clock
453+
*
454+
* @param hw Beginning address of the peripheral registers.
455+
* @param enable true to enable, false to disable
456+
*/
457+
static inline void gpspi_flash_ll_enable_clock(spi_dev_t *hw, bool enable)
458+
{
459+
(void) hw;
460+
PCR.spi2_clkm_conf.spi2_clkm_en = enable;
461+
}
462+
429463
#ifdef __cplusplus
430464
}
431465
#endif

‎components/hal/esp32c61/include/hal/spi_flash_ll.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ extern "C" {
2626
#define spi_flash_ll_calculate_clock_reg(host_id, clock_div) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_calculate_clock_reg(clock_div) \
2727
: gpspi_flash_ll_calculate_clock_reg(clock_div))
2828

29-
#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ)
29+
#define spi_flash_ll_get_source_clock_freq_mhz(host_id) (((host_id)<=SPI1_HOST) ? spimem_flash_ll_get_source_freq_mhz() : -1)
3030

3131
#define spi_flash_ll_get_hw(host_id) (((host_id)<=SPI1_HOST ? (spi_dev_t*) spimem_flash_ll_get_hw(host_id) \
3232
: gpspi_flash_ll_get_hw(host_id)))

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