Standardize on W/E/S/N for on-chip directions everywhere in the project.

[wanda-phi]

This will require converting an ungodly amount of code. Here's a little progress tracker:

• common code
• siliconblue
• xc2000/xc3000/xc4000/xc5200
  • rename col_lio/row_bio/...
  • rename all tiles (and some terms)
  • rename col_q[lr] and row_q[bt]
• virtex
  • rename col_lio/row_bio/...
  • fix up LIO/RIO in Chip display
  • rename IO.* tiles
  • rename CNR.* tiles
  • rename LBRAM/RBRAM tiles (and MBRAM while we're at it)
  • rename BRAM_BOT/BRAM_TOP tiles
  • rename DLL.BOT/DLL.TOP tiles
  • rename CLKB*/CLKT* tiles
  • rename CLKL/CLKR tiles
  • rename CLKV_BRAM_BOT/TOP tiles
• virtex2
  • rename DcmPairKind::*
  • rename col_left/row_bot/...
  • rename get_iob_data_<edge>
  • rename ColumnIoKind::* and RowIoKind::* (remember associated printout)
  • rename corner tiles
  • rename INT.IOI.S3A.* tiles
  • rename IOI.S3A.* tiles
  • rename INT.IOI.CLK_* and IOI.CLK_* tiles
  • rename DCM.S3E.* tiles
  • rename DCMCONN.* tiles
  • rename *PPC tiles
  • rename INTF.GT.* tiles
  • rename GIGABIT* tiles
  • rename LLV.CLKLR.* terms
  • rename LLH.CLK[BT].S3A tiles
  • rename CLKLR.S3E.* terms
  • rename CLK[BTLR] tiles
  • rename GCLKC.[BT] tiles
  • rename IOBS.* tiles
  • rename btile_lrterm and btile_btterm
  • rename btile_btspine
  • rename btile_llv_[bt]
• spartan6
• virtex4
• virtex5
• virtex6
• virtex7
• ultrascale
• versal