[hardware] Generate new registers and waive linter checks

Author: mbertuletti

.github/workflows/lint.yml

@@ -67,8 +67,10 @@ jobs:
         fi
     - name: Check for trailing whitespaces and tabs
       run: |
-        git diff --check $base HEAD --          \
-            ':(exclude)**.def'                  \
-            ':(exclude)**.patch'                \
-            ':(exclude)toolchain/**'            \
-            ':(exclude)software/riscv-tests/**'
+        git diff --check $base HEAD --                       \
+            ':(exclude)**.def'                               \
+            ':(exclude)**.patch'                             \
+            ':(exclude)toolchain/**'                         \
+            ':(exclude)software/riscv-tests/**'              \
+            ':(exclude)software/runtime/control_registers.h' \
+            ':(exclude)hardware/src/control_registers/*.sv'

hardware/src/control_registers/Makefile

@@ -7,8 +7,9 @@
 SHELL = /usr/bin/env bash
 ROOT_DIR := $(patsubst %/,%, $(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
 RUNTIME_DIR := $(abspath $(ROOT_DIR)/../../../software/runtime)
+BENDER := $(ROOT_DIR)/../../../install/bender/bender
 
-regtool ?= $(abspath $(ROOT_DIR)/../../deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py)
+regtool ?= $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py
 
 RTL := $(patsubst $(ROOT_DIR)/%.hjson,%,$(shell find $(ROOT_DIR) -name "*.hjson"))
 

hardware/src/control_registers/control_registers_reg_pkg.sv

@@ -1,6 +1,6 @@
-// Copyright 2024 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
 //
 // Register Package auto-generated by `reggen` containing data structure
 
@@ -209,3 +209,4 @@ package control_registers_reg_pkg;
   };
 
 endpackage
+

hardware/src/control_registers/control_registers_reg_top.sv

@@ -1,6 +1,6 @@
-// Copyright 2024 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
 //
 // Register Top module auto-generated by `reggen`
 
@@ -993,7 +993,6 @@ module control_registers_reg_top #(
 
 endmodule
 
-/* verilator lint_off DECLFILENAME */
 module control_registers_reg_top_intf
 #(
   parameter int AW = 7,
@@ -1021,12 +1020,12 @@ module control_registers_reg_top_intf
 
   reg_bus_req_t s_reg_req;
   reg_bus_rsp_t s_reg_rsp;
-
+  
   // Assign SV interface to structs
   `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave)
   `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp)
 
-
+  
 
   control_registers_reg_top #(
     .reg_req_t(reg_bus_req_t),
@@ -1041,6 +1040,7 @@ module control_registers_reg_top_intf
     .hw2reg, // Read
     .devmode_i
   );
-
+  
 endmodule
-/* verilator lint_on DECLFILENAME */
+
+

scripts/license-checker.hjson

@@ -21,6 +21,8 @@
     'software/riscv-tests/*'
     'hardware/deps/*'
     'hardware/tb/dpi/elfloader.cpp'
+    'hardware/src/control_registers/control_registers_reg_pkg.sv'
+    'hardware/src/control_registers/control_registers_reg_top.sv'
     'scripts/run_clang_format.py'
     'toolchain/*'
   ]

software/runtime/control_registers.h

@@ -4,7 +4,7 @@
 // Copyright 2024 ETH Zurich and University of Bologna.
 
 // Licensing information found in source file:
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// 
 // SPDX-License-Identifier: SHL-0.51
 
 #ifndef _CONTROL_REGISTERS_REG_DEFS_