From 9b9c9ffbc0b1170ac8cf5d12ad30944b440615a3 Mon Sep 17 00:00:00 2001
From: Zexin Fu <zexifu@iis.ee.ethz.ch>
Date: Thu, 9 Oct 2025 17:29:30 +0200
Subject: [PATCH 01/13] [bender] Remove all hardware submodules, switch to
 bender.

---
 .gitmodules                        | 33 --------------------
 Bender.lock                        | 50 +++++++++++++++---------------
 hardware/deps/.gitignore           | 11 +++++++
 hardware/deps/apb                  |  1 -
 hardware/deps/axi                  |  1 -
 hardware/deps/cluster_icache       |  1 -
 hardware/deps/cluster_interconnect |  1 -
 hardware/deps/common_cells         |  1 -
 hardware/deps/common_verification  |  1 -
 hardware/deps/dram_rtl_sim         |  1 -
 hardware/deps/fpnew                |  1 -
 hardware/deps/fpu_div_sqrt_mvp     |  1 -
 hardware/deps/register_interface   |  1 -
 hardware/deps/tech_cells_generic   |  1 -
 14 files changed, 36 insertions(+), 69 deletions(-)
 create mode 100644 hardware/deps/.gitignore
 delete mode 160000 hardware/deps/apb
 delete mode 160000 hardware/deps/axi
 delete mode 160000 hardware/deps/cluster_icache
 delete mode 160000 hardware/deps/cluster_interconnect
 delete mode 160000 hardware/deps/common_cells
 delete mode 160000 hardware/deps/common_verification
 delete mode 160000 hardware/deps/dram_rtl_sim
 delete mode 160000 hardware/deps/fpnew
 delete mode 160000 hardware/deps/fpu_div_sqrt_mvp
 delete mode 160000 hardware/deps/register_interface
 delete mode 160000 hardware/deps/tech_cells_generic

diff --git a/.gitmodules b/.gitmodules
index b3535cc46..fdcc03686 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -10,39 +10,6 @@
 [submodule "toolchain/verilator"]
 	path = toolchain/verilator
 	url = https://github.com/verilator/verilator.git
-[submodule "hardware/deps/axi"]
-	path = hardware/deps/axi
-	url = https://github.com/pulp-platform/axi.git
-[submodule "hardware/deps/cluster_interconnect"]
-	path = hardware/deps/cluster_interconnect
-	url = https://github.com/pulp-platform/cluster_interconnect.git
-[submodule "hardware/deps/common_cells"]
-	path = hardware/deps/common_cells
-	url = https://github.com/pulp-platform/common_cells.git
-[submodule "hardware/deps/common_verification"]
-	path = hardware/deps/common_verification
-	url = https://github.com/pulp-platform/common_verification.git
-[submodule "hardware/deps/register_interface"]
-	path = hardware/deps/register_interface
-	url = https://github.com/pulp-platform/register_interface.git
-[submodule "hardware/deps/tech_cells_generic"]
-	path = hardware/deps/tech_cells_generic
-	url = https://github.com/pulp-platform/tech_cells_generic.git
 [submodule "toolchain/riscv-opcodes"]
 	path = toolchain/riscv-opcodes
 	url = https://github.com/pulp-platform/riscv-opcodes.git
-[submodule "hardware/deps/apb"]
-	path = hardware/deps/apb
-	url = https://github.com/pulp-platform/apb.git
-[submodule "hardware/deps/fpnew"]
-	path = hardware/deps/fpnew
-	url = https://github.com/pulp-platform/cvfpu.git
-[submodule "hardware/deps/fpu_div_sqrt_mvp"]
-	path = hardware/deps/fpu_div_sqrt_mvp
-	url = https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
-[submodule "hardware/deps/dram_rtl_sim"]
-	path = hardware/deps/dram_rtl_sim
-	url = https://github.com/pulp-platform/dram_rtl_sim.git
-[submodule "hardware/deps/cluster_icache"]
-	path = hardware/deps/cluster_icache
-	url = https://github.com/pulp-platform/cluster_icache.git
diff --git a/Bender.lock b/Bender.lock
index d03aa7ff6..89d566b7e 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -1,16 +1,16 @@
 packages:
   apb:
-    revision: null
-    version: null
+    revision: 77ddf073f194d44b9119949d2421be59789e69ae
+    version: 0.2.4
     source:
-      Path: hardware/deps/apb
+      Git: https://github.com/pulp-platform/apb.git
     dependencies:
     - common_cells
   axi:
-    revision: null
-    version: null
+    revision: ac5deb3ff086aa34b168f392c051e92603d6c0e2
+    version: 0.39.2
     source:
-      Path: hardware/deps/axi
+      Git: https://github.com/pulp-platform/axi.git
     dependencies:
     - common_cells
     - common_verification
@@ -26,39 +26,39 @@ packages:
     - scm
     - tech_cells_generic
   cluster_interconnect:
-    revision: null
-    version: null
+    revision: 7d0a4f8acae71a583a6713cab5554e60b9bb8d27
+    version: 1.2.1
     source:
-      Path: hardware/deps/cluster_interconnect
+      Git: https://github.com/pulp-platform/cluster_interconnect.git
     dependencies:
     - common_cells
   common_cells:
-    revision: null
-    version: null
+    revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239
+    version: 1.33.0
     source:
-      Path: hardware/deps/common_cells
+      Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
     - common_verification
     - tech_cells_generic
   common_verification:
-    revision: null
-    version: null
+    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
+    version: 0.2.3
     source:
-      Path: hardware/deps/common_verification
+      Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   fpnew:
-    revision: null
+    revision: 9481d57c161bb160fd294eae07279082bff06698
     version: null
     source:
-      Path: hardware/deps/fpnew
+      Git: https://github.com/pulp-platform/cvfpu.git
     dependencies:
     - common_cells
     - fpu_div_sqrt_mvp
   fpu_div_sqrt_mvp:
-    revision: null
+    revision: 917dd79cb2dc1a8f43df1a84e0e4231508a980e9
     version: null
     source:
-      Path: hardware/deps/fpu_div_sqrt_mvp
+      Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
     dependencies:
     - common_cells
   idma:
@@ -72,10 +72,10 @@ packages:
     - common_verification
     - register_interface
   register_interface:
-    revision: null
-    version: null
+    revision: e25b36670ff7aab3402f40efcc2b11ee0f31cf19
+    version: 0.4.3
     source:
-      Path: hardware/deps/register_interface
+      Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
     - apb
     - axi
@@ -104,9 +104,9 @@ packages:
     - axi
     - common_cells
   tech_cells_generic:
-    revision: null
-    version: null
+    revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
+    version: 0.2.13
     source:
-      Path: hardware/deps/tech_cells_generic
+      Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:
     - common_verification
diff --git a/hardware/deps/.gitignore b/hardware/deps/.gitignore
new file mode 100644
index 000000000..31dd415f6
--- /dev/null
+++ b/hardware/deps/.gitignore
@@ -0,0 +1,11 @@
+apb/
+axi/
+cluster_icache/
+cluster_interconnect/
+common_cells/
+common_verification/
+dram_rtl_sim/
+fpnew/
+fpu_div_sqrt_mvp/
+register_interface/
+tech_cells_generic/
\ No newline at end of file
diff --git a/hardware/deps/apb b/hardware/deps/apb
deleted file mode 160000
index 77ddf073f..000000000
--- a/hardware/deps/apb
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 77ddf073f194d44b9119949d2421be59789e69ae
diff --git a/hardware/deps/axi b/hardware/deps/axi
deleted file mode 160000
index ac5deb3ff..000000000
--- a/hardware/deps/axi
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit ac5deb3ff086aa34b168f392c051e92603d6c0e2
diff --git a/hardware/deps/cluster_icache b/hardware/deps/cluster_icache
deleted file mode 160000
index 0e1fb6751..000000000
--- a/hardware/deps/cluster_icache
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 0e1fb6751d9684d968ba7fb40836e6118b448ecd
diff --git a/hardware/deps/cluster_interconnect b/hardware/deps/cluster_interconnect
deleted file mode 160000
index 7d0a4f8ac..000000000
--- a/hardware/deps/cluster_interconnect
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 7d0a4f8acae71a583a6713cab5554e60b9bb8d27
diff --git a/hardware/deps/common_cells b/hardware/deps/common_cells
deleted file mode 160000
index 13f28aa00..000000000
--- a/hardware/deps/common_cells
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 13f28aa0021fc22c0d01a12d618fda58d2c93239
diff --git a/hardware/deps/common_verification b/hardware/deps/common_verification
deleted file mode 160000
index 9c07fa860..000000000
--- a/hardware/deps/common_verification
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9c07fa860593b2caabd9b5681740c25fac04b878
diff --git a/hardware/deps/dram_rtl_sim b/hardware/deps/dram_rtl_sim
deleted file mode 160000
index 15caf378b..000000000
--- a/hardware/deps/dram_rtl_sim
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 15caf378b6981527f5b0600304c4c748ffd09e97
diff --git a/hardware/deps/fpnew b/hardware/deps/fpnew
deleted file mode 160000
index 9481d57c1..000000000
--- a/hardware/deps/fpnew
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9481d57c161bb160fd294eae07279082bff06698
diff --git a/hardware/deps/fpu_div_sqrt_mvp b/hardware/deps/fpu_div_sqrt_mvp
deleted file mode 160000
index 917dd79cb..000000000
--- a/hardware/deps/fpu_div_sqrt_mvp
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 917dd79cb2dc1a8f43df1a84e0e4231508a980e9
diff --git a/hardware/deps/register_interface b/hardware/deps/register_interface
deleted file mode 160000
index e25b36670..000000000
--- a/hardware/deps/register_interface
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit e25b36670ff7aab3402f40efcc2b11ee0f31cf19
diff --git a/hardware/deps/tech_cells_generic b/hardware/deps/tech_cells_generic
deleted file mode 160000
index 7968dd6e6..000000000
--- a/hardware/deps/tech_cells_generic
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 7968dd6e6180df2c644636bc6d2908a49f2190cf

From ce5a8131e6959fe90c770bd5c5634f8cb4adbdf3 Mon Sep 17 00:00:00 2001
From: Zexin Fu <zexifu@iis.ee.ethz.ch>
Date: Thu, 9 Oct 2025 17:58:12 +0200
Subject: [PATCH 02/13] [bender] Always checkout bender deps if necessary when
 any Makefile target is called. Also add clean-deps target to clean all the
 deps.

---
 Makefile          | 33 ++++++++++++++++++++++++++++++++-
 hardware/Makefile | 30 ++++++++++++++++++++++++++++++
 2 files changed, 62 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 0d2aff6e9..ecd51a5e3 100644
--- a/Makefile
+++ b/Makefile
@@ -21,6 +21,7 @@ ISA_SIM_INSTALL_DIR   ?= ${INSTALL_DIR}/riscv-isa-sim
 LLVM_INSTALL_DIR      ?= ${INSTALL_DIR}/llvm
 HALIDE_INSTALL_DIR    ?= ${INSTALL_DIR}/halide
 BENDER_INSTALL_DIR    ?= ${INSTALL_DIR}/bender
+BENDER                ?= ${BENDER_INSTALL_DIR}/bender
 VERILATOR_INSTALL_DIR ?= ${INSTALL_DIR}/verilator
 RISCV_TESTS_DIR       ?= ${ROOT_DIR}/${SOFTWARE_DIR}/riscv-tests
 
@@ -54,6 +55,36 @@ else
   CLANG_LDFLAGS  := ""
 endif
 
+# Update Bender dependencies
+BENDER_ROOT ?= $(ROOT_DIR)/hardware/deps
+
+# Ensure both Bender dependencies and (essential) submodules are checked out
+$(BENDER_ROOT)/.mempool_deps: $(BENDER_INSTALL_DIR)/bender
+	cd $(ROOT_DIR) && $(BENDER) checkout
+	@touch $@
+
+# Make sure dependencies are more up-to-date than any targets run
+ifeq ($(shell test -f $(BENDER_ROOT)/.mempool_deps && echo 1),)
+-include $(BENDER_ROOT)/.mempool_deps
+endif
+
+# Running this target will reset dependencies (without updating the checked-in Bender.lock)
+.PHONY: clean-deps
+clean-deps:
+	cd $(BENDER_ROOT) && rm -rf \
+		apb \
+		axi \
+		cluster_icache \
+		cluster_interconnect \
+		common_cells \
+		common_verification \
+		dram_rtl_sim \
+		fpnew \
+		fpu_div_sqrt_mvp \
+		register_interface \
+		tech_cells_generic
+	rm -f $(BENDER_ROOT)/.mempool_deps
+
 # Default target
 all: toolchain riscv-isa-sim halide
 
@@ -152,7 +183,7 @@ $(VERILATOR_INSTALL_DIR)/bin/verilator: toolchain/verilator Makefile
 # Update and patch hardware dependencies for MemPool
 # Previous changes will be stashed. Clear all the stashes with `git stash clear`
 .PHONY: update-deps
-update-deps: setup-dram
+update-deps: setup-dram $(BENDER_ROOT)/.mempool_deps
 	for dep in $(shell git config --file .gitmodules --get-regexp path \
 	| awk '/hardware/{ print $$2 }'); do \
 	  git -C $${dep} diff --quiet || { echo $${dep}; git -C $${dep} stash -u; }; \
diff --git a/hardware/Makefile b/hardware/Makefile
index 1a78620c7..40f574ca6 100644
--- a/hardware/Makefile
+++ b/hardware/Makefile
@@ -166,6 +166,36 @@ cpp_defs += -DAXI_DATA_WIDTH=$(axi_data_width)
 
 .DEFAULT_GOAL := compile
 
+# Update Bender dependencies
+BENDER_ROOT ?= $(ROOT_DIR)/deps
+
+# Ensure both Bender dependencies and (essential) submodules are checked out
+$(BENDER_ROOT)/.mempool_deps: $(bender)
+	cd $(ROOT_DIR)/.. $(bender) checkout
+	@touch $@
+
+# Make sure dependencies are more up-to-date than any targets run
+ifeq ($(shell test -f $(BENDER_ROOT)/.mempool_deps && echo 1),)
+-include $(BENDER_ROOT)/.mempool_deps
+endif
+
+# Running this target will reset dependencies (without updating the checked-in Bender.lock)
+.PHONY: clean-deps
+clean-deps:
+	cd $(BENDER_ROOT) && rm -rf \
+		apb \
+		axi \
+		cluster_icache \
+		cluster_interconnect \
+		common_cells \
+		common_verification \
+		dram_rtl_sim \
+		fpnew \
+		fpu_div_sqrt_mvp \
+		register_interface \
+		tech_cells_generic
+	rm -f $(BENDER_ROOT)/.mempool_deps
+
 # Build path
 $(buildpath):
 	mkdir -p $(buildpath)

From a0450d4d9d49c5c97cd78fe937707de4104a24e5 Mon Sep 17 00:00:00 2001
From: Zexin Fu <zexifu@iis.ee.ethz.ch>
Date: Thu, 9 Oct 2025 17:59:19 +0200
Subject: [PATCH 03/13] [bender] Remove hardware git submodule init in ci
 scripts.

---
 .github/workflows/ci.yml | 2 +-
 .gitlab/.gitlab-ci.yml   | 4 ----
 hardware/deps/.gitignore | 3 ++-
 3 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index af457d92b..2c935ff94 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -247,7 +247,7 @@ jobs:
       run: pip install -r python-requirements.txt
     - name: Build Control Registers
       run: |
-        git submodule update --init --recursive -- hardware/deps/register_interface
+        make bender
         git apply hardware/deps/patches/register_interface.patch
         make -C hardware/src/control_registers clean
         make -C hardware/src/control_registers all
diff --git a/.gitlab/.gitlab-ci.yml b/.gitlab/.gitlab-ci.yml
index a49145bc6..610eae831 100644
--- a/.gitlab/.gitlab-ci.yml
+++ b/.gitlab/.gitlab-ci.yml
@@ -100,7 +100,6 @@ verilator-model:
         ln -s $VERILATOR_ROOT/share/verilator/include $VERILATOR_ROOT/include
         ln -s $VERILATOR_ROOT/share/verilator/bin/verilator_includer $VERILATOR_ROOT/bin/verilator_includer
         # Build the verilator model
-        git submodule update --init --recursive -- hardware/deps/*
         make update-deps
         make -C hardware $ROOT_DIR/hardware/verilator_build/Vmempool_tb_verilator
         $CI_PROJECT_DIR/scripts/memora_retry.sh insert verilator-model
@@ -112,7 +111,6 @@ verilator-model:
 hardware:
   stage: test
   script:
-    - git submodule update --init --recursive -- hardware/deps/*
     - make update-deps
     - make -C hardware compile
   needs: []
@@ -157,7 +155,6 @@ check-opcodes:
     - cd software/apps/baremetal
     - make COMPILER=${COMPILER} all
     - cd ../..
-    - git submodule update --init --recursive -- hardware/deps/*
     - make update-deps
     - cd hardware
     - |
@@ -192,7 +189,6 @@ apps-halide:
     - cd software/apps/halide
     - make COMPILER=${COMPILER} all
     - cd ../..
-    - git submodule update --init --recursive -- hardware/deps/*
     - make update-deps
     - cd hardware
     - app=apps/halide/2d_convolution make simc
diff --git a/hardware/deps/.gitignore b/hardware/deps/.gitignore
index 31dd415f6..6fe621be2 100644
--- a/hardware/deps/.gitignore
+++ b/hardware/deps/.gitignore
@@ -8,4 +8,5 @@ dram_rtl_sim/
 fpnew/
 fpu_div_sqrt_mvp/
 register_interface/
-tech_cells_generic/
\ No newline at end of file
+tech_cells_generic/
+.mempool_deps
\ No newline at end of file

From c75ecb9c094e7bd2417593ce9d138a5b9b94585b Mon Sep 17 00:00:00 2001
From: Zexin Fu <zexifu@iis.ee.ethz.ch>
Date: Thu, 9 Oct 2025 18:56:58 +0200
Subject: [PATCH 04/13] [bender] Add the dramsys git submodule back.

---
 .gitlab/.gitlab-ci.yml     | 4 ++++
 .gitmodules                | 3 +++
 Makefile                   | 1 -
 hardware/Makefile          | 1 -
 hardware/deps/.gitignore   | 1 -
 hardware/deps/dram_rtl_sim | 1 +
 6 files changed, 8 insertions(+), 3 deletions(-)
 create mode 160000 hardware/deps/dram_rtl_sim

diff --git a/.gitlab/.gitlab-ci.yml b/.gitlab/.gitlab-ci.yml
index 610eae831..a49145bc6 100644
--- a/.gitlab/.gitlab-ci.yml
+++ b/.gitlab/.gitlab-ci.yml
@@ -100,6 +100,7 @@ verilator-model:
         ln -s $VERILATOR_ROOT/share/verilator/include $VERILATOR_ROOT/include
         ln -s $VERILATOR_ROOT/share/verilator/bin/verilator_includer $VERILATOR_ROOT/bin/verilator_includer
         # Build the verilator model
+        git submodule update --init --recursive -- hardware/deps/*
         make update-deps
         make -C hardware $ROOT_DIR/hardware/verilator_build/Vmempool_tb_verilator
         $CI_PROJECT_DIR/scripts/memora_retry.sh insert verilator-model
@@ -111,6 +112,7 @@ verilator-model:
 hardware:
   stage: test
   script:
+    - git submodule update --init --recursive -- hardware/deps/*
     - make update-deps
     - make -C hardware compile
   needs: []
@@ -155,6 +157,7 @@ check-opcodes:
     - cd software/apps/baremetal
     - make COMPILER=${COMPILER} all
     - cd ../..
+    - git submodule update --init --recursive -- hardware/deps/*
     - make update-deps
     - cd hardware
     - |
@@ -189,6 +192,7 @@ apps-halide:
     - cd software/apps/halide
     - make COMPILER=${COMPILER} all
     - cd ../..
+    - git submodule update --init --recursive -- hardware/deps/*
     - make update-deps
     - cd hardware
     - app=apps/halide/2d_convolution make simc
diff --git a/.gitmodules b/.gitmodules
index fdcc03686..c94d2c972 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -13,3 +13,6 @@
 [submodule "toolchain/riscv-opcodes"]
 	path = toolchain/riscv-opcodes
 	url = https://github.com/pulp-platform/riscv-opcodes.git
+[submodule "hardware/deps/dram_rtl_sim"]
+	path = hardware/deps/dram_rtl_sim
+	url = https://github.com/pulp-platform/dram_rtl_sim.git
diff --git a/Makefile b/Makefile
index ecd51a5e3..8259c171a 100644
--- a/Makefile
+++ b/Makefile
@@ -78,7 +78,6 @@ clean-deps:
 		cluster_interconnect \
 		common_cells \
 		common_verification \
-		dram_rtl_sim \
 		fpnew \
 		fpu_div_sqrt_mvp \
 		register_interface \
diff --git a/hardware/Makefile b/hardware/Makefile
index 40f574ca6..af3b8b21b 100644
--- a/hardware/Makefile
+++ b/hardware/Makefile
@@ -189,7 +189,6 @@ clean-deps:
 		cluster_interconnect \
 		common_cells \
 		common_verification \
-		dram_rtl_sim \
 		fpnew \
 		fpu_div_sqrt_mvp \
 		register_interface \
diff --git a/hardware/deps/.gitignore b/hardware/deps/.gitignore
index 6fe621be2..1a6a617a3 100644
--- a/hardware/deps/.gitignore
+++ b/hardware/deps/.gitignore
@@ -4,7 +4,6 @@ cluster_icache/
 cluster_interconnect/
 common_cells/
 common_verification/
-dram_rtl_sim/
 fpnew/
 fpu_div_sqrt_mvp/
 register_interface/
diff --git a/hardware/deps/dram_rtl_sim b/hardware/deps/dram_rtl_sim
new file mode 160000
index 000000000..2cac4a9e1
--- /dev/null
+++ b/hardware/deps/dram_rtl_sim
@@ -0,0 +1 @@
+Subproject commit 2cac4a9e12a60537567276b539ab6c919c87b5dc

From 8e0e45ba27430f8081cdde707a74a5d46050228f Mon Sep 17 00:00:00 2001
From: mbertuletti <mbertuletti@iis.ee.ethz.ch>
Date: Tue, 9 Dec 2025 15:15:26 +0100
Subject: [PATCH 05/13] [bender] Change update_opcodes target

---
 .github/workflows/ci.yml          |  4 ++--
 .gitlab/.gitlab-ci.yml            |  4 ++--
 hardware/Makefile                 | 10 +++++-----
 software/Makefile                 |  6 +++---
 software/apps/baremetal/Makefile  |  6 +++---
 software/apps/omp/Makefile        |  6 +++---
 software/apps/systolic/Makefile   |  6 +++---
 software/tests/baremetal/Makefile |  6 +++---
 software/tests/omp/Makefile       |  6 +++---
 9 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 2c935ff94..1f4af73c1 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -259,7 +259,7 @@ jobs:
     - uses: actions/checkout@v4
     - name: Regenerate opcodes
       run: |
-        make update_opcodes
+        make update-opcodes
         git diff --exit-code
 
   ####################
@@ -518,7 +518,7 @@ jobs:
       run: |
         # Don't regenerate previously build artifacts
         sudo apt install device-tree-compiler
-        make update_opcodes
+        make update-opcodes
         touch $GITHUB_WORKSPACE/software/runtime/encoding.h
         touch $GITHUB_WORKSPACE/hardware/src/bootrom.sv
         touch $GITHUB_WORKSPACE/hardware/deps/snitch/src/riscv_instr.sv
diff --git a/.gitlab/.gitlab-ci.yml b/.gitlab/.gitlab-ci.yml
index a49145bc6..ca8b351d2 100644
--- a/.gitlab/.gitlab-ci.yml
+++ b/.gitlab/.gitlab-ci.yml
@@ -138,7 +138,7 @@ check-control-registers:
 check-opcodes:
   stage: test
   script:
-    - make update_opcodes
+    - make update-opcodes
     - git diff --exit-code
 
 # Software tests
@@ -218,7 +218,7 @@ unit-tests:
     - $CI_PROJECT_DIR/scripts/memora_retry.sh get tc-riscv-gcc
     - $CI_PROJECT_DIR/scripts/memora_retry.sh get riscv-isa-sim
     - $CI_PROJECT_DIR/scripts/memora_retry.sh get verilator-model
-    - make update_opcodes
+    - make update-opcodes
     - touch $ROOT_DIR/software/runtime/encoding.h
     - touch $ROOT_DIR/hardware/src/bootrom.sv
     - touch $ROOT_DIR/hardware/deps/snitch/src/riscv_instr.sv
diff --git a/hardware/Makefile b/hardware/Makefile
index af3b8b21b..fad652d29 100644
--- a/hardware/Makefile
+++ b/hardware/Makefile
@@ -214,7 +214,7 @@ $(buildpath)/$(library):
 
 # Compilation
 .PHONY: compile
-compile: dpi lib $(buildpath) $(buildpath)/compile.tcl update_opcodes
+compile: dpi lib $(buildpath) $(buildpath)/compile.tcl update-opcodes
 $(buildpath)/compile.tcl: $(bender) $(config_mk) Makefile $(MEMPOOL_DIR)/Bender.yml $(shell find {src,tb,deps} -type f)
 	$(bender) script vsim --vlog-arg="$(vlog_args)" $(vlog_defs) -t rtl -t mempool_vsim > $(buildpath)/compile.tcl
 	echo "exit" >> $(buildpath)/compile.tcl
@@ -251,7 +251,7 @@ $(buildpath)/$(dpi_library)/mempool_dpi.so: $(dpi)
 
 # Elaboration
 .PHONY: elabvcs
-elabvcs: dpivcs $(buildpath) $(buildpath)/compilevcs.sh update_opcodes
+elabvcs: dpivcs $(buildpath) $(buildpath)/compilevcs.sh update-opcodes
 $(buildpath)/compilevcs.sh: $(bender) $(config_mk) Makefile $(MEMPOOL_DIR)/Bender.yml $(shell find {src,tb,deps} -type f)
 	$(bender) script vcs --vlogan-bin="$(vcs_cmd) vlogan" --vlog-arg="$(vlogan_args)" $(vlog_defs) -t rtl -t mempool_vsim > $(buildpath)/compilevcs.sh
 	echo "exit" >> $(buildpath)/compilevcs.sh
@@ -448,10 +448,10 @@ $(CONTROL_REG_DIR)/control_registers_reg_top.sv: $(CONTROL_REG_DIR)/control_regi
 	make -C $(CONTROL_REG_DIR) all
 
 # Clean targets
-.PHONY: clean clean-dasm clean-trace update_opcodes
+.PHONY: clean clean-dasm clean-trace update-opcodes
 
-update_opcodes:
-	make -C $(MEMPOOL_DIR) update_opcodes
+update-opcodes:
+	make -C $(MEMPOOL_DIR) update-opcodes
 
 clean:
 	@rm -rf $(buildpath)
diff --git a/software/Makefile b/software/Makefile
index df661a674..dde34d0b3 100644
--- a/software/Makefile
+++ b/software/Makefile
@@ -63,7 +63,7 @@ $(eval $(call rtl_mempool_tests_template,rv32ua))
 $(eval $(call rtl_mempool_tests_template,rv32uxpulpimg))
 endif
 
-riscv-tests: update_opcodes $(RISCV_TESTS)
+riscv-tests: update-opcodes $(RISCV_TESTS)
 
 clean-riscv-test:
 	rm -vf $(RUNTIME)
@@ -72,8 +72,8 @@ clean-riscv-test:
 	rm -vf $(addsuffix .dump,$(RISCV_TESTS))
 
 # Helper targets
-update_opcodes:
-	make -C $(MEMPOOL_DIR) update_opcodes
+update-opcodes:
+	make -C $(MEMPOOL_DIR) update-opcodes
 
 .PHONY: clean
 clean: clean-tests clean-apps clean-riscv-test
diff --git a/software/apps/baremetal/Makefile b/software/apps/baremetal/Makefile
index bb640dfde..73953dc07 100644
--- a/software/apps/baremetal/Makefile
+++ b/software/apps/baremetal/Makefile
@@ -37,14 +37,14 @@ all_llvm: $(ALL_LLVM)
 $(APPS): % : $(BIN_DIR)/% $(APPS_DIR)/Makefile $(shell find $(RUNTIME_DIR)/**.{S,c,h,ld} -type f)
 
 .PHONY: $(BINARIES)
-$(BINARIES): $(BIN_DIR)/%: %/main.c.o $(RUNTIME) $(LINKER_SCRIPT) data_%.h update_opcodes
+$(BINARIES): $(BIN_DIR)/%: %/main.c.o $(RUNTIME) $(LINKER_SCRIPT) data_%.h update-opcodes
 	mkdir -p $(dir $@)
 	$(RISCV_CC) -Iinclude -o $@ $< $(RUNTIME) $(RISCV_LDFLAGS) -T$(RUNTIME_DIR)/link.ld
 	$(RISCV_OBJDUMP) $(RISCV_OBJDUMP_FLAGS) -D $@ > $@.dump
 
 # Helper targets
-update_opcodes:
-	make -C $(MEMPOOL_DIR) update_opcodes
+update-opcodes:
+	make -C $(MEMPOOL_DIR) update-opcodes
 
 .PHONY: clean
 clean:
diff --git a/software/apps/omp/Makefile b/software/apps/omp/Makefile
index cece16052..a95de2898 100644
--- a/software/apps/omp/Makefile
+++ b/software/apps/omp/Makefile
@@ -28,14 +28,14 @@ all: $(BINARIES)
 $(APPS): % : $(BIN_DIR)/% $(APPS_DIR)/Makefile $(shell find $(RUNTIME_DIR)/**.{S,c,h,ld} -type f)
 
 .PHONY: $(BINARIES)
-$(BINARIES): $(BIN_DIR)/%: %/main.c.o $(RUNTIME) $(OMP_RUNTIME) $(LINKER_SCRIPT) update_opcodes
+$(BINARIES): $(BIN_DIR)/%: %/main.c.o $(RUNTIME) $(OMP_RUNTIME) $(LINKER_SCRIPT) update-opcodes
 	mkdir -p $(dir $@)
 	$(RISCV_CC) -Iinclude $(RISCV_LDFLAGS) -o $@ $< $(RUNTIME) $(OMP_RUNTIME) -T$(RUNTIME_DIR)/link.ld
 	$(RISCV_OBJDUMP) $(RISCV_OBJDUMP_FLAGS) -D $@ > $@.dump
 
 # Helper targets
-update_opcodes:
-	make -C $(MEMPOOL_DIR) update_opcodes
+update-opcodes:
+	make -C $(MEMPOOL_DIR) update-opcodes
 
 .PHONY: clean
 clean:
diff --git a/software/apps/systolic/Makefile b/software/apps/systolic/Makefile
index 93e960434..939803b26 100644
--- a/software/apps/systolic/Makefile
+++ b/software/apps/systolic/Makefile
@@ -24,7 +24,7 @@ $(APPS): % : $(BIN_DIR)/% $(APPS_DIR)/Makefile $(shell find $(RUNTIME_DIR)/**.{S
 # Check if the config is set to systolic
 ifeq ($(config),systolic)
 .PHONY: $(BINARIES)
-$(BINARIES): $(BIN_DIR)/%: %/main.c.o $(RUNTIME) $(LINKER_SCRIPT) data_%.h update_opcodes
+$(BINARIES): $(BIN_DIR)/%: %/main.c.o $(RUNTIME) $(LINKER_SCRIPT) data_%.h update-opcodes
 	mkdir -p $(dir $@)
 	$(RISCV_CC) -Iinclude $(RISCV_LDFLAGS) -o $@ $< $(RUNTIME) -T$(RUNTIME_DIR)/link.ld
 	$(RISCV_OBJDUMP) $(RISCV_OBJDUMP_FLAGS) -D $@ > $@.dump
@@ -36,8 +36,8 @@ $(BINARIES):
 endif
 
 # Helper targets
-update_opcodes:
-	make -C $(MEMPOOL_DIR) update_opcodes
+update-opcodes:
+	make -C $(MEMPOOL_DIR) update-opcodes
 
 .PHONY: clean
 clean:
diff --git a/software/tests/baremetal/Makefile b/software/tests/baremetal/Makefile
index 71dac7ce9..53af85328 100644
--- a/software/tests/baremetal/Makefile
+++ b/software/tests/baremetal/Makefile
@@ -24,14 +24,14 @@ all: $(TESTS)
 $(TESTS): % : $(BIN_DIR)/% $(TESTS_DIR)/Makefile $(shell find $(RUNTIME_DIR)/**.{S,c,h,ld} -type f)
 
 .PHONY: $(BINARIES)
-$(BINARIES): $(BIN_DIR)/%: %/main.c.o $(RUNTIME) $(LINKER_SCRIPT) data_%.h update_opcodes
+$(BINARIES): $(BIN_DIR)/%: %/main.c.o $(RUNTIME) $(LINKER_SCRIPT) data_%.h update-opcodes
 	mkdir -p $(dir $@)
 	$(RISCV_CC) -Iinclude $(RISCV_LDFLAGS) -o $@ $< $(RUNTIME) -T$(RUNTIME_DIR)/link.ld
 	$(RISCV_OBJDUMP) $(RISCV_OBJDUMP_FLAGS) -D $@ > $@.dump
 
 # Helper targets
-update_opcodes:
-	make -C $(MEMPOOL_DIR) update_opcodes
+update-opcodes:
+	make -C $(MEMPOOL_DIR) update-opcodes
 
 .PHONY: clean
 clean:
diff --git a/software/tests/omp/Makefile b/software/tests/omp/Makefile
index 73a61326f..128d21027 100644
--- a/software/tests/omp/Makefile
+++ b/software/tests/omp/Makefile
@@ -28,14 +28,14 @@ all: $(BINARIES)
 $(TESTS): % : $(BIN_DIR)/% $(TESTS_DIR)/Makefile $(shell find $(RUNTIME_DIR)/**.{S,c,h,ld} -type f)
 
 .PHONY: $(BINARIES)
-$(BINARIES): $(BIN_DIR)/%: %/main.c.o $(RUNTIME) $(OMP_RUNTIME) $(LINKER_SCRIPT) update_opcodes
+$(BINARIES): $(BIN_DIR)/%: %/main.c.o $(RUNTIME) $(OMP_RUNTIME) $(LINKER_SCRIPT) update-opcodes
 	mkdir -p $(dir $@)
 	$(RISCV_CC) -Iinclude $(RISCV_LDFLAGS) -o $@ $< $(RUNTIME) $(OMP_RUNTIME) -T$(RUNTIME_DIR)/link.ld
 	$(RISCV_OBJDUMP) $(RISCV_OBJDUMP_FLAGS) -D $@ > $@.dump
 
 # Helper targets
-update_opcodes:
-	make -C $(MEMPOOL_DIR) update_opcodes
+update-opcodes:
+	make -C $(MEMPOOL_DIR) update-opcodes
 
 .PHONY: clean
 clean:

From f27b4fc2a5d0e42cd93b19e6a84217fad516e9eb Mon Sep 17 00:00:00 2001
From: mbertuletti <mbertuletti@iis.ee.ethz.ch>
Date: Tue, 9 Dec 2025 15:53:55 +0100
Subject: [PATCH 06/13] [bender] Remove unuseful targets for benderized
 dependencies

---
 Bender.yml              |   2 +-
 Makefile                | 159 +++++++++++++++++++++-------------------
 README.md               |   7 ++
 hardware/Makefile       |  33 +--------
 hardware/deps/README.md |  32 --------
 5 files changed, 94 insertions(+), 139 deletions(-)
 delete mode 100644 hardware/deps/README.md

diff --git a/Bender.yml b/Bender.yml
index 8d6913a8e..bc7610bc7 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -14,7 +14,7 @@ dependencies:
   reqrsp_interface:     { path: "hardware/deps/reqrsp_interface"                                             }
   snitch:               { path: "hardware/deps/snitch"                                                       }
   tech_cells_generic:   { git: "https://github.com/pulp-platform/tech_cells_generic.git",   version: 0.2.13  }
-  fpnew:                { git: "https://github.com/pulp-platform/cvfpu.git",                rev: pulp-v0.1.3 }
+  fpnew:                { git: "https://github.com/pulp-platform/cvfpu.git",                rev: "9481d57"   }
   cluster_icache:       { git: "https://github.com/pulp-platform/cluster_icache.git",       version: 0.1.1   }
 
 workspace:
diff --git a/Makefile b/Makefile
index 8259c171a..64d4a163f 100644
--- a/Makefile
+++ b/Makefile
@@ -22,6 +22,7 @@ LLVM_INSTALL_DIR      ?= ${INSTALL_DIR}/llvm
 HALIDE_INSTALL_DIR    ?= ${INSTALL_DIR}/halide
 BENDER_INSTALL_DIR    ?= ${INSTALL_DIR}/bender
 BENDER                ?= ${BENDER_INSTALL_DIR}/bender
+BENDER_ROOT 					?= $(ROOT_DIR)/hardware/deps
 VERILATOR_INSTALL_DIR ?= ${INSTALL_DIR}/verilator
 RISCV_TESTS_DIR       ?= ${ROOT_DIR}/${SOFTWARE_DIR}/riscv-tests
 
@@ -55,55 +56,11 @@ else
   CLANG_LDFLAGS  := ""
 endif
 
-# Update Bender dependencies
-BENDER_ROOT ?= $(ROOT_DIR)/hardware/deps
+#############
+# Toolchain #
+#############
 
-# Ensure both Bender dependencies and (essential) submodules are checked out
-$(BENDER_ROOT)/.mempool_deps: $(BENDER_INSTALL_DIR)/bender
-	cd $(ROOT_DIR) && $(BENDER) checkout
-	@touch $@
-
-# Make sure dependencies are more up-to-date than any targets run
-ifeq ($(shell test -f $(BENDER_ROOT)/.mempool_deps && echo 1),)
--include $(BENDER_ROOT)/.mempool_deps
-endif
-
-# Running this target will reset dependencies (without updating the checked-in Bender.lock)
-.PHONY: clean-deps
-clean-deps:
-	cd $(BENDER_ROOT) && rm -rf \
-		apb \
-		axi \
-		cluster_icache \
-		cluster_interconnect \
-		common_cells \
-		common_verification \
-		fpnew \
-		fpu_div_sqrt_mvp \
-		register_interface \
-		tech_cells_generic
-	rm -f $(BENDER_ROOT)/.mempool_deps
-
-# Default target
-all: toolchain riscv-isa-sim halide
-
-# Halide
-halide:
-	mkdir -p $(HALIDE_INSTALL_DIR)
-	cd toolchain/halide && mkdir -p build && cd build; \
-	$(CMAKE) \
-		-DLLVM_DIR=$(LLVM_INSTALL_DIR)/lib/cmake/llvm \
-		-DCMAKE_INSTALL_PREFIX=$(HALIDE_INSTALL_DIR) \
-		-DCMAKE_INSTALL_LIBDIR=lib \
-		-DCMAKE_CXX_COMPILER=$(CXX) \
-		-DCMAKE_C_COMPILER=$(CC) \
-		-DWITH_PYTHON_BINDINGS=OFF \
-		-DCMAKE_BUILD_TYPE=Release \
-		.. && \
-	make -j4 all && \
-	make install
-
-# Toolchain
+# Compilers
 toolchain: tc-riscv-gcc tc-llvm
 
 tc-riscv-gcc:
@@ -132,10 +89,47 @@ tc-llvm:
 	make -j6 all && \
 	make install
 
-riscv-isa-sim: update_opcodes
+# Halide
+halide:
+	mkdir -p $(HALIDE_INSTALL_DIR)
+	cd toolchain/halide && mkdir -p build && cd build; \
+	$(CMAKE) \
+		-DLLVM_DIR=$(LLVM_INSTALL_DIR)/lib/cmake/llvm \
+		-DCMAKE_INSTALL_PREFIX=$(HALIDE_INSTALL_DIR) \
+		-DCMAKE_INSTALL_LIBDIR=lib \
+		-DCMAKE_CXX_COMPILER=$(CXX) \
+		-DCMAKE_C_COMPILER=$(CC) \
+		-DWITH_PYTHON_BINDINGS=OFF \
+		-DCMAKE_BUILD_TYPE=Release \
+		.. && \
+	make -j4 all && \
+	make install
+
+# Opcodes
+update-opcodes: software/runtime/encoding.h hardware/deps/snitch/src/riscv_instr.sv
+
+software/runtime/encoding.h: toolchain/riscv-opcodes/*
+	make -C toolchain/riscv-opcodes encoding_out.h
+	mv toolchain/riscv-opcodes/encoding_out.h $@
+	ln -fsr $@ toolchain/riscv-isa-sim/riscv/encoding.h
+	ln -fsr $@ software/riscv-tests/env/encoding.h #this will change when riscv-tests is a submodule
+
+hardware/deps/snitch/src/riscv_instr.sv: toolchain/riscv-opcodes/*
+	make -C toolchain/riscv-opcodes inst.sverilog
+	mv toolchain/riscv-opcodes/inst.sverilog $@
+
+toolchain/riscv-opcodes/*:
+	git submodule update --init --recursive -- toolchain/riscv-opcodes
+
+# Tracing
+riscv-isa-sim: update-opcodes
 	cd toolchain/riscv-isa-sim && mkdir -p build && cd build; \
 	../configure --prefix=$(ISA_SIM_INSTALL_DIR) && make && make install
 
+#########
+# Tests #
+#########
+
 # Unit tests for verification
 .PHONY: riscv-tests build-riscv-tests clean-riscv-tests
 
@@ -145,7 +139,7 @@ riscv-tests: build-riscv-tests
 	config=minpool make -C $(SOFTWARE_DIR) riscv-tests && \
 	config=minpool make -C hardware verilate_test
 
-build-riscv-tests: update_opcodes
+build-riscv-tests: update-opcodes
 	cd $(RISCV_TESTS_DIR); \
 	autoconf && ./configure --with-xlen=32 --prefix=$$(pwd)/target && \
 	make isa -j4 && make install && \
@@ -156,8 +150,13 @@ clean-riscv-tests:
 	$(MAKE) -C $(SOFTWARE_DIR) clean
 	$(MAKE) -C $(RISCV_TESTS_DIR) clean
 
+###################
+# HW Dependencies #
+###################
+
 # Bender
 bender: check-bender
+
 check-bender:
 	@if [ -x $(BENDER_INSTALL_DIR)/bender ]; then \
 		req="bender $(BENDER_VERSION)"; \
@@ -172,6 +171,31 @@ $(BENDER_INSTALL_DIR)/bender:
 	mkdir -p $(BENDER_INSTALL_DIR) && cd $(BENDER_INSTALL_DIR) && \
 	curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh -s -- $(BENDER_VERSION)
 
+# Update and patch hardware dependencies for MemPool
+.PHONY: update-deps
+update-deps: check-bender
+	$(BENDER) checkout
+	git apply hardware/deps/patches/*
+
+# Running this target will reset dependencies (without updating the checked-in Bender.lock)
+.PHONY: clean-deps
+clean-deps:
+	cd $(BENDER_ROOT) && rm -rf \
+		apb \
+		axi \
+		cluster_icache \
+		cluster_interconnect \
+		common_cells \
+		common_verification \
+		fpnew \
+		fpu_div_sqrt_mvp \
+		register_interface \
+		tech_cells_generic
+
+##############
+# Simulation #
+##############
+
 # Verilator
 verilator: $(VERILATOR_INSTALL_DIR)/bin/verilator
 $(VERILATOR_INSTALL_DIR)/bin/verilator: toolchain/verilator Makefile
@@ -179,16 +203,9 @@ $(VERILATOR_INSTALL_DIR)/bin/verilator: toolchain/verilator Makefile
 	autoconf && CC=$(CC) CXX=$(CXX) ./configure --prefix=$(VERILATOR_INSTALL_DIR) $(VERILATOR_CI) && \
 	make -j4 && make install
 
-# Update and patch hardware dependencies for MemPool
-# Previous changes will be stashed. Clear all the stashes with `git stash clear`
-.PHONY: update-deps
-update-deps: setup-dram $(BENDER_ROOT)/.mempool_deps
-	for dep in $(shell git config --file .gitmodules --get-regexp path \
-	| awk '/hardware/{ print $$2 }'); do \
-	  git -C $${dep} diff --quiet || { echo $${dep}; git -C $${dep} stash -u; }; \
-	  git submodule update --init --recursive -- $${dep}; \
-	done
-	git apply hardware/deps/patches/*
+###########
+# DRAMsys #
+###########
 
 # Build, update and patch the DRAMsys submodule
 $(eval DRAM_PATH=$(realpath $(shell git config --file .gitmodules --get-regexp dram_rtl_sim.path | awk '/hardware/{ print $$2 }')))
@@ -225,30 +242,18 @@ setup-dram: config-dram
 		make -j; \
 	fi
 
-# Helper targets
+##########
+# Helper #
+##########
+
 .PHONY: clean format apps
 
 apps:
 	make -C $(SOFTWARE_DIR) apps
 
-update_opcodes: software/runtime/encoding.h hardware/deps/snitch/src/riscv_instr.sv
-
-software/runtime/encoding.h: toolchain/riscv-opcodes/*
-	make -C toolchain/riscv-opcodes encoding_out.h
-	mv toolchain/riscv-opcodes/encoding_out.h $@
-	ln -fsr $@ toolchain/riscv-isa-sim/riscv/encoding.h
-	ln -fsr $@ software/riscv-tests/env/encoding.h #this will change when riscv-tests is a submodule
-
-hardware/deps/snitch/src/riscv_instr.sv: toolchain/riscv-opcodes/*
-	make -C toolchain/riscv-opcodes inst.sverilog
-	mv toolchain/riscv-opcodes/inst.sverilog $@
-
-toolchain/riscv-opcodes/*:
-	git submodule update --init --recursive -- toolchain/riscv-opcodes
-
 format:
 	$(ROOT_DIR)/scripts/run_clang_format.py --clang-format-executable=$(LLVM_INSTALL_DIR)/bin/clang-format -i -r $(ROOT_DIR)
 	find ./software/data -name '*.py' -exec autopep8 --in-place --aggressive {} +
 
-clean: clean-riscv-tests
+clean: clean-riscv-tests clean-deps
 	rm -rf $(INSTALL_DIR)
diff --git a/README.md b/README.md
index 264914b35..bee14d106 100644
--- a/README.md
+++ b/README.md
@@ -71,6 +71,13 @@ We use [Bender](https://github.com/pulp-platform/bender) to generate our simulat
 make bender
 ```
 
+To checkout the hardware dependencies using Bender run:
+
+```bash
+# Update hardware dependencies
+make update-deps
+```
+
 The RTL simulation, or more specifically, the tracing in the simulation, relies on the SPIKE simulator. To build it, run the following command in the project's directory:
 
 ```bash
diff --git a/hardware/Makefile b/hardware/Makefile
index fad652d29..ed705f661 100644
--- a/hardware/Makefile
+++ b/hardware/Makefile
@@ -166,35 +166,6 @@ cpp_defs += -DAXI_DATA_WIDTH=$(axi_data_width)
 
 .DEFAULT_GOAL := compile
 
-# Update Bender dependencies
-BENDER_ROOT ?= $(ROOT_DIR)/deps
-
-# Ensure both Bender dependencies and (essential) submodules are checked out
-$(BENDER_ROOT)/.mempool_deps: $(bender)
-	cd $(ROOT_DIR)/.. $(bender) checkout
-	@touch $@
-
-# Make sure dependencies are more up-to-date than any targets run
-ifeq ($(shell test -f $(BENDER_ROOT)/.mempool_deps && echo 1),)
--include $(BENDER_ROOT)/.mempool_deps
-endif
-
-# Running this target will reset dependencies (without updating the checked-in Bender.lock)
-.PHONY: clean-deps
-clean-deps:
-	cd $(BENDER_ROOT) && rm -rf \
-		apb \
-		axi \
-		cluster_icache \
-		cluster_interconnect \
-		common_cells \
-		common_verification \
-		fpnew \
-		fpu_div_sqrt_mvp \
-		register_interface \
-		tech_cells_generic
-	rm -f $(BENDER_ROOT)/.mempool_deps
-
 # Build path
 $(buildpath):
 	mkdir -p $(buildpath)
@@ -206,6 +177,7 @@ $(bender):
 ################
 # Modelsim     #
 ################
+
 # Library
 .PHONY: lib
 lib: $(buildpath) $(buildpath)/$(library)
@@ -297,6 +269,7 @@ $(buildpath)/$(dpi_library)/mempool_vcs_dpi.so: $(dpi_vcs)
 ################
 # Verilator    #
 ################
+
 VERILATOR_SRC   := $(ROOT_DIR)/tb/verilator
 VERILATOR_LIBS  := $(shell find $(VERILATOR_SRC) -name "*.cc" -print | sort)
 VERILATOR_INCS  := $(shell find $(VERILATOR_SRC) -name "cpp" -print | sort)
@@ -351,6 +324,7 @@ verilate: $(VERILATOR_EXE) $(buildpath) Makefile
 #############
 # Lint      #
 #############
+
 .PHONY: lint spyglass/tmp/files
 
 SNPS_SG ?= spyglass-2022.06
@@ -408,6 +382,7 @@ tracevis:
 ############################
 # Unit tests simulation    #
 ############################
+
 TESTS_DIR := $(abspath $(ROOT_DIR)/../software/riscv-tests/isa)
 include $(TESTS_DIR)/snitch_isa.mk
 
diff --git a/hardware/deps/README.md b/hardware/deps/README.md
deleted file mode 100644
index 6b384f0b2..000000000
--- a/hardware/deps/README.md
+++ /dev/null
@@ -1,32 +0,0 @@
-# Hardware Dependencies
-
-All hardware dependencies in this folder are git repositories themselves that are flattened into this repository. They are managed by [Bender](https://github.com/fabianschuiki/bender) instead of git submodules or subtrees. This allows us to have a flat repository where all changes are visible in a single repository. The downside is that changes to the dependencies need to be pulled/pushed to the upstream repository manually. The flow to do so is described here.
-
-## Add new dependency
-
-1. To add a new dependency, simply add it to the `Bender.yml` file and execute `bender update`. This will check the new dependencies and create a new `Bender.lock` entry. You can double check the lock file to make sure the correct commit will be checked out.
-2. Execute a bender command, like `bender script vsim`, which will trigger Bender to actually check out the repository.
-3. Remove the `.git` folder in the new dependency, which will flatten it into the main repository.
-4. Add all the files from the submodule to git and create a commit. Make sure the main repository's `.gitignore` file is not excluding important files from the new dependency.
-
-## Push changes to upstream
-
-If you modify a dependency to implement some fixes or upgrades you want to contribute back to the upstream repository use the following flow. We use the `axi` dependency as an example.
-
-1. Make sure the main repository is in a clean state and everything is checked in.
-2. Delete the folder containing your dependency: `rm -rf deps/axi`
-3. Check out the folder with Bender. This will restore the folder from the last point you synchronized it with the upstream repository. `make build`
-4. Reset the changes in the dependency folder that you just introduced by checking out the last synchronization point. `git checkout deps/axi`
-5. Now you restored the `.git` folder linked with the correct commit. However, the remote will be in the `.bender` folder. Add the upstream remote you want to push to. `cd deps/axi; git remote add upstream https://github.com/pulp-platform/axi`
-6. Create/Checkout a branch and add the changes, push them to the upstream repository.
-7. Remote the `.git` folder in the repo to reflatten the repository and add a commit updating the `Bender.lock` file to indicate the synchronization point.
-
-## Pull changes from upstream
-
-1. Make sure the main repository is in a clean state and everything is checked in.
-2. Make sure your dependency has no changes compared to the last synchronization point that are not yet merged with the upstream repository.
-3. Delete the folder containing your dependency: `rm -rf deps/axi`
-4. Change the `Bender.yml`/`Bender.lock` to the version you want to upgrade to.
-5. Pull the dependency through Bender. `make build`
-6. Remove the dependency's `.git` folder.
-7. Commit the changes to the dependency and the changes to the `Bender.*` files to the main repository.

From 9f7fa9dcc0cac253a5a3b17b99144fe0eded0483 Mon Sep 17 00:00:00 2001
From: mbertuletti <mbertuletti@iis.ee.ethz.ch>
Date: Tue, 9 Dec 2025 16:02:11 +0100
Subject: [PATCH 07/13] [ci] Update with new Bender target to update
 dependencies

---
 .github/workflows/ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 1f4af73c1..45031c501 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -248,7 +248,7 @@ jobs:
     - name: Build Control Registers
       run: |
         make bender
-        git apply hardware/deps/patches/register_interface.patch
+        make update-deps
         make -C hardware/src/control_registers clean
         make -C hardware/src/control_registers all
         git diff --ignore-submodules=dirty --exit-code

From 0e5e6b8a3d6396a08f56d7747312034b0641619e Mon Sep 17 00:00:00 2001
From: mbertuletti <mbertuletti@iis.ee.ethz.ch>
Date: Wed, 10 Dec 2025 09:51:24 +0100
Subject: [PATCH 08/13] [tb] Add wrapper for L2 pre-loading in simulation

---
 Bender.yml                         |   1 +
 hardware/src/mempool_system.sv     |   2 +-
 hardware/src/tc_sram_simwrapper.sv | 111 +++++++++++++++++++++++++++++
 hardware/tb/mempool_tb.sv          |   2 +-
 4 files changed, 114 insertions(+), 2 deletions(-)
 create mode 100644 hardware/src/tc_sram_simwrapper.sv

diff --git a/Bender.yml b/Bender.yml
index bc7610bc7..392b0e64b 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -48,6 +48,7 @@ sources:
   # Level 5
   - hardware/src/ctrl_registers.sv
   # Level 6
+  - hardware/src/tc_sram_simwrapper.sv
   - hardware/src/mempool_system.sv
 
   - target: mempool_vsim
diff --git a/hardware/src/mempool_system.sv b/hardware/src/mempool_system.sv
index 98c6fde07..c4610486f 100644
--- a/hardware/src/mempool_system.sv
+++ b/hardware/src/mempool_system.sv
@@ -407,7 +407,7 @@ module mempool_system
     );
     assign mem_rsp_chan[i].error = 1'b0;
 
-    tc_sram #(
+    tc_sram_simwrapper #(
       .DataWidth(L2BankWidth   ),
       .NumWords (L2BankNumWords),
       .NumPorts (1             ),
diff --git a/hardware/src/tc_sram_simwrapper.sv b/hardware/src/tc_sram_simwrapper.sv
new file mode 100644
index 000000000..5f17aadc0
--- /dev/null
+++ b/hardware/src/tc_sram_simwrapper.sv
@@ -0,0 +1,111 @@
+// Copyright 2021 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+module tc_sram_simwrapper #(
+  parameter int unsigned NumWords     = 32'd1024, // Number of Words in data array
+  parameter int unsigned DataWidth    = 32'd128,  // Data signal width
+  parameter int unsigned ByteWidth    = 32'd8,    // Width of a data byte
+  parameter int unsigned NumPorts     = 32'd2,    // Number of read and write ports
+  parameter int unsigned Latency      = 32'd1,    // Latency when the read data is available
+  parameter              SimInit      = "none",   // Simulation initialization
+  parameter bit          PrintSimCfg  = 1'b0,     // Print configuration
+  parameter              ImplKey      = "none",   // Reference to specific implementation
+  // DEPENDENT PARAMETERS, DO NOT OVERWRITE!
+  parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1,
+  parameter int unsigned BeWidth   = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div
+  parameter type         addr_t    = logic [AddrWidth-1:0],
+  parameter type         data_t    = logic [DataWidth-1:0],
+  parameter type         be_t      = logic [BeWidth-1:0]
+) (
+  input  logic                 clk_i,      // Clock
+  input  logic                 rst_ni,     // Asynchronous reset active low
+  // input ports
+  input  logic  [NumPorts-1:0] req_i,      // request
+  input  logic  [NumPorts-1:0] we_i,       // write enable
+  input  addr_t [NumPorts-1:0] addr_i,     // request address
+  input  data_t [NumPorts-1:0] wdata_i,    // write data
+  input  be_t   [NumPorts-1:0] be_i,       // write byte enable
+  // output ports
+  output data_t [NumPorts-1:0] rdata_o     // read data
+);
+
+
+  tc_sram #(
+    .DataWidth(DataWidth  ),
+    .NumWords (NumWords   ),
+    .NumPorts (NumPorts   ),
+    .SimInit  (SimInit    )
+  ) i_sram (
+    .clk_i  (clk_i        ),
+    .rst_ni (rst_ni       ),
+    .req_i  (req_i        ),
+    .we_i   (we_i         ),
+    .addr_i (addr_i       ),
+    .wdata_i(wdata_i      ),
+    .be_i   (be_i         ),
+    .rdata_o(rdata_o      )
+  );
+
+
+/**
+ * Memory loader for simulation
+ *
+ * Include this file in a memory primitive to load a memory array from
+ * simulation.
+ *
+ * Requirements:
+ * - A memory array named `sram`.
+ * - A parameter `DataWidth` giving the memory width (word size) in bit.
+ * - A parameter `NumWords` giving the memory depth in words.
+ */
+
+`ifndef SYNTHESIS
+  // Task for loading 'sram' with SystemVerilog system task $readmemh()
+  export "DPI-C" task simutil_memload;
+
+  task simutil_memload;
+    input string file;
+    $readmemh(file, i_sram.sram);
+  endtask
+
+  // Function for setting a specific element in |sram|
+  // Returns 1 (true) for success, 0 (false) for errors.
+  export "DPI-C" function simutil_set_mem;
+
+  function int simutil_set_mem(input int index, input bit [1023:0] val);
+
+    // Function will only work for memories <= 1024 bits
+    if (DataWidth > 1024) begin
+      return 0;
+    end
+
+    if (index >= NumWords) begin
+      return 0;
+    end
+
+    i_sram.sram[index] = val[DataWidth-1:0];
+    return 1;
+  endfunction
+
+  // Function for getting a specific element in |sram|
+  export "DPI-C" function simutil_get_mem;
+
+  function int simutil_get_mem(input int index, output bit [1023:0] val);
+
+    // Function will only work for memories <= 1024 bits
+    if (DataWidth > 1024) begin
+      return 0;
+    end
+
+    if (index >= NumWords) begin
+      return 0;
+    end
+
+    val = 0;
+    val[DataWidth-1:0] = i_sram.sram[index];
+    return 1;
+  endfunction
+`endif
+
+endmodule
diff --git a/hardware/tb/mempool_tb.sv b/hardware/tb/mempool_tb.sv
index 9d6a04928..aef26c62a 100644
--- a/hardware/tb/mempool_tb.sv
+++ b/hardware/tb/mempool_tb.sv
@@ -341,7 +341,7 @@ module mempool_tb;
               mem_row[8 * b +: 8] = buffer[(bank + w * NumL2Banks) * L2BankBeWidth + b];
             end
             if (address >= dut.L2MemoryBaseAddr && address < dut.L2MemoryEndAddr) begin
-              dut.gen_l2_banks[bank].l2_mem.init_val[(address - dut.L2MemoryBaseAddr + (w << L2ByteOffset)) >> L2ByteOffset] = mem_row;
+              dut.gen_l2_banks[bank].l2_mem.i_sram.init_val[(address - dut.L2MemoryBaseAddr + (w << L2ByteOffset)) >> L2ByteOffset] = mem_row;
             end else begin
               $display("Cannot initialize address %x, which doesn't fall into the L2 region.", address);
             end

From 71181503d73a06bf2179279da3d4d4806b5b99e3 Mon Sep 17 00:00:00 2001
From: mbertuletti <mbertuletti@iis.ee.ethz.ch>
Date: Wed, 10 Dec 2025 10:36:45 +0100
Subject: [PATCH 09/13] [tb] Do not stop on verilator warnings

---
 hardware/tb/verilator/verilator.flags | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hardware/tb/verilator/verilator.flags b/hardware/tb/verilator/verilator.flags
index 3477dfd52..6d912de9d 100644
--- a/hardware/tb/verilator/verilator.flags
+++ b/hardware/tb/verilator/verilator.flags
@@ -15,7 +15,7 @@
 -Wno-UNUSED
 -Wno-UNOPTFLAT
 // Continue despite warnings
-// -Wno-fatal
+-Wno-fatal
 
 // C++ mode and flags
 --cc

From 5e2950ac7bd715f2fec1ac111aebdc2592a49e4e Mon Sep 17 00:00:00 2001
From: mbertuletti <mbertuletti@iis.ee.ethz.ch>
Date: Wed, 10 Dec 2025 10:42:30 +0100
Subject: [PATCH 10/13] [bender] Remove patches

---
 Bender.yml                                    |   3 -
 Makefile                                      |  18 +--
 .../deps/patches/register_interface.patch     |  98 ---------------
 .../deps/patches/tech_cells_generic.patch     | 118 ------------------
 4 files changed, 1 insertion(+), 236 deletions(-)
 delete mode 100644 hardware/deps/patches/register_interface.patch
 delete mode 100644 hardware/deps/patches/tech_cells_generic.patch

diff --git a/Bender.yml b/Bender.yml
index 392b0e64b..180981a8e 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -17,9 +17,6 @@ dependencies:
   fpnew:                { git: "https://github.com/pulp-platform/cvfpu.git",                rev: "9481d57"   }
   cluster_icache:       { git: "https://github.com/pulp-platform/cluster_icache.git",       version: 0.1.1   }
 
-workspace:
-  checkout_dir: "./hardware/deps"
-
 export_include_dirs:
   - hardware/include
 
diff --git a/Makefile b/Makefile
index 64d4a163f..aae1e7c4b 100644
--- a/Makefile
+++ b/Makefile
@@ -171,26 +171,10 @@ $(BENDER_INSTALL_DIR)/bender:
 	mkdir -p $(BENDER_INSTALL_DIR) && cd $(BENDER_INSTALL_DIR) && \
 	curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh -s -- $(BENDER_VERSION)
 
-# Update and patch hardware dependencies for MemPool
+# Update hardware dependencies for MemPool
 .PHONY: update-deps
 update-deps: check-bender
 	$(BENDER) checkout
-	git apply hardware/deps/patches/*
-
-# Running this target will reset dependencies (without updating the checked-in Bender.lock)
-.PHONY: clean-deps
-clean-deps:
-	cd $(BENDER_ROOT) && rm -rf \
-		apb \
-		axi \
-		cluster_icache \
-		cluster_interconnect \
-		common_cells \
-		common_verification \
-		fpnew \
-		fpu_div_sqrt_mvp \
-		register_interface \
-		tech_cells_generic
 
 ##############
 # Simulation #
diff --git a/hardware/deps/patches/register_interface.patch b/hardware/deps/patches/register_interface.patch
deleted file mode 100644
index 04bea1d5f..000000000
--- a/hardware/deps/patches/register_interface.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-diff --git a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl
-index 1c5520a..77619d9 100644
---- a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl
-+++ b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_pkg.sv.tpl
-@@ -1,6 +1,6 @@
--// Copyright lowRISC contributors.
--// Licensed under the Apache License, Version 2.0, see LICENSE for details.
--// SPDX-License-Identifier: Apache-2.0
-+// Copyright 2024 ETH Zurich and University of Bologna.
-+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-+// SPDX-License-Identifier: SHL-0.51
- //
- // Register Package auto-generated by `reggen` containing data structure
- <%
-@@ -344,4 +344,3 @@ ${reg_data_for_iface(iface_name, iface_desc, for_iface, rb)}\
- % endfor
- 
- endpackage
--
-diff --git a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl
-index bfab87f..2b2764e 100644
---- a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl
-+++ b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/reggen/reg_top.sv.tpl
-@@ -1,6 +1,6 @@
--// Copyright lowRISC contributors.
--// Licensed under the Apache License, Version 2.0, see LICENSE for details.
--// SPDX-License-Identifier: Apache-2.0
-+// Copyright 2024 ETH Zurich and University of Bologna.
-+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-+// SPDX-License-Identifier: SHL-0.51
- //
- // Register Top module auto-generated by `reggen`
- <%
-@@ -534,6 +534,7 @@ ${rdata_gen(f, r.name.lower() + "_" + f.name.lower())}\
- endmodule
- 
- % if use_reg_iface:
-+/* verilator lint_off DECLFILENAME */
- module ${mod_name}_intf
- #(
-   parameter int AW = ${addr_width},
-@@ -568,7 +569,7 @@ module ${mod_name}_intf
- 
-   reg_bus_req_t s_reg_req;
-   reg_bus_rsp_t s_reg_rsp;
--  
-+
-   // Assign SV interface to structs
-   `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave)
-   `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp)
-@@ -580,9 +581,9 @@ module ${mod_name}_intf
-     `REG_BUS_ASSIGN_TO_REQ(s_reg_win_req[i], regbus_win_mst[i])
-     `REG_BUS_ASSIGN_FROM_RSP(regbus_win_mst[i], s_reg_win_rsp[i])
-   end
--  
-+
- % endif
--  
-+
- 
-   ${mod_name} #(
-     .reg_req_t(reg_bus_req_t),
-@@ -605,11 +606,10 @@ module ${mod_name}_intf
- % endif
-     .devmode_i
-   );
--  
--endmodule
- 
-+endmodule
-+/* verilator lint_on DECLFILENAME */
- % endif
--
- <%def name="str_bits_sv(bits)">\
- % if bits.msb != bits.lsb:
- ${bits.msb}:${bits.lsb}\
-diff --git a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py
-index f7e117a..767c839 100755
---- a/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py
-+++ b/hardware/deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py
-@@ -210,7 +210,7 @@ def main():
-         found_lunder = None
-         copy = re.compile(r'.*(copyright.*)|(.*\(c\).*)', re.IGNORECASE)
-         spdx = re.compile(r'.*(SPDX-License-Identifier:.+)')
--        lunder = re.compile(r'.*(Licensed under.+)', re.IGNORECASE)
-+        lunder = re.compile(r'.*(Solderpad.*)|(Apache.*)', re.IGNORECASE)
-         for line in srcfull.splitlines():
-             mat = copy.match(line)
-             if mat is not None:
-@@ -225,7 +225,7 @@ def main():
-             src_lic = found_lunder
-         if found_spdx:
-             if src_lic is None:
--                src_lic = '\n' + found_spdx
-+                src_lic = found_spdx
-             else:
-                 src_lic += '\n' + found_spdx
- 
diff --git a/hardware/deps/patches/tech_cells_generic.patch b/hardware/deps/patches/tech_cells_generic.patch
deleted file mode 100644
index 7f06aac42..000000000
--- a/hardware/deps/patches/tech_cells_generic.patch
+++ /dev/null
@@ -1,118 +0,0 @@
-diff --git a/hardware/deps/tech_cells_generic/src/deprecated/pulp_clk_cells.sv b/hardware/deps/tech_cells_generic/src/deprecated/pulp_clk_cells.sv
-index 53ad07f..4f47d47 100644
---- a/hardware/deps/tech_cells_generic/src/deprecated/pulp_clk_cells.sv
-+++ b/hardware/deps/tech_cells_generic/src/deprecated/pulp_clk_cells.sv
-@@ -98,9 +98,9 @@ module pulp_clock_delay(
-   input  logic in_i,
-   output logic out_o
- );
--
-+  /* verilator lint_off ASSIGNDLY */
-   assign #(300ps) out_o = in_i;
--
-+  /* verilator lint_on ASSIGNDLY */
- endmodule
- `endif
- 
-diff --git a/hardware/deps/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv b/hardware/deps/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv
-index 5c95b55..88e9707 100644
---- a/hardware/deps/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv
-+++ b/hardware/deps/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv
-@@ -41,4 +41,4 @@ module pulp_clock_gating_async #(
-     .clk_o
-   );
- 
--endmodule
-\ No newline at end of file
-+endmodule
-diff --git a/hardware/deps/tech_cells_generic/src/rtl/tc_clk.sv b/hardware/deps/tech_cells_generic/src/rtl/tc_clk.sv
-index 3ab329e..491c719 100644
---- a/hardware/deps/tech_cells_generic/src/rtl/tc_clk.sv
-+++ b/hardware/deps/tech_cells_generic/src/rtl/tc_clk.sv
-@@ -43,10 +43,11 @@ module tc_clk_gating #(
- );
- 
-   logic clk_en;
--
-+  /* verilator lint_off COMBDLY */
-   always_latch begin
-     if (clk_i == 1'b0) clk_en <= en_i | test_en_i;
-   end
-+  /* verilator lint_on COMBDLY */
- 
-   assign clk_o = clk_i & clk_en;
- 
-diff --git a/hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv b/hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv
-index b702a11..a3cb149 100644
---- a/hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv
-+++ b/hardware/deps/tech_cells_generic/src/rtl/tc_sram.sv
-@@ -242,4 +242,69 @@ module tc_sram #(
- `endif
- `endif
- // pragma translate_on
-+
-+// Copyright lowRISC contributors.
-+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-+// SPDX-License-Identifier: Apache-2.0
-+
-+/**
-+ * Memory loader for simulation
-+ *
-+ * Include this file in a memory primitive to load a memory array from
-+ * simulation.
-+ *
-+ * Requirements:
-+ * - A memory array named `sram`.
-+ * - A parameter `DataWidth` giving the memory width (word size) in bit.
-+ * - A parameter `NumWords` giving the memory depth in words.
-+ */
-+
-+`ifndef SYNTHESIS
-+  // Task for loading 'sram' with SystemVerilog system task $readmemh()
-+  export "DPI-C" task simutil_memload;
-+
-+  task simutil_memload;
-+    input string file;
-+    $readmemh(file, sram);
-+  endtask
-+
-+  // Function for setting a specific element in |sram|
-+  // Returns 1 (true) for success, 0 (false) for errors.
-+  export "DPI-C" function simutil_set_mem;
-+
-+  function int simutil_set_mem(input int index, input bit [1023:0] val);
-+
-+    // Function will only work for memories <= 1024 bits
-+    if (DataWidth > 1024) begin
-+      return 0;
-+    end
-+
-+    if (index >= NumWords) begin
-+      return 0;
-+    end
-+
-+    sram[index] = val[DataWidth-1:0];
-+    return 1;
-+  endfunction
-+
-+  // Function for getting a specific element in |sram|
-+  export "DPI-C" function simutil_get_mem;
-+
-+  function int simutil_get_mem(input int index, output bit [1023:0] val);
-+
-+    // Function will only work for memories <= 1024 bits
-+    if (DataWidth > 1024) begin
-+      return 0;
-+    end
-+
-+    if (index >= NumWords) begin
-+      return 0;
-+    end
-+
-+    val = 0;
-+    val[DataWidth-1:0] = sram[index];
-+    return 1;
-+  endfunction
-+`endif
-+
- endmodule

From 8cb5805c9b23a1e92618b435575623617fcfa2e3 Mon Sep 17 00:00:00 2001
From: mbertuletti <mbertuletti@iis.ee.ethz.ch>
Date: Wed, 10 Dec 2025 10:54:10 +0100
Subject: [PATCH 11/13] [hardware] Generate new registers and waive linter
 checks

---
 .github/workflows/lint.yml                       | 12 +++++++-----
 hardware/src/control_registers/Makefile          |  3 ++-
 .../control_registers_reg_pkg.sv                 |  7 ++++---
 .../control_registers_reg_top.sv                 | 16 ++++++++--------
 scripts/license-checker.hjson                    |  2 ++
 software/runtime/control_registers.h             |  2 +-
 6 files changed, 24 insertions(+), 18 deletions(-)

diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml
index c152e7f0a..7c36ae8a6 100644
--- a/.github/workflows/lint.yml
+++ b/.github/workflows/lint.yml
@@ -67,8 +67,10 @@ jobs:
         fi
     - name: Check for trailing whitespaces and tabs
       run: |
-        git diff --check $base HEAD --          \
-            ':(exclude)**.def'                  \
-            ':(exclude)**.patch'                \
-            ':(exclude)toolchain/**'            \
-            ':(exclude)software/riscv-tests/**'
+        git diff --check $base HEAD --                       \
+            ':(exclude)**.def'                               \
+            ':(exclude)**.patch'                             \
+            ':(exclude)toolchain/**'                         \
+            ':(exclude)software/riscv-tests/**'              \
+            ':(exclude)software/runtime/control_registers.h' \
+            ':(exclude)hardware/src/control_registers/*.sv'
diff --git a/hardware/src/control_registers/Makefile b/hardware/src/control_registers/Makefile
index 84d1d6319..07914e669 100644
--- a/hardware/src/control_registers/Makefile
+++ b/hardware/src/control_registers/Makefile
@@ -7,8 +7,9 @@
 SHELL = /usr/bin/env bash
 ROOT_DIR := $(patsubst %/,%, $(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
 RUNTIME_DIR := $(abspath $(ROOT_DIR)/../../../software/runtime)
+BENDER := $(ROOT_DIR)/../../../install/bender/bender
 
-regtool ?= $(abspath $(ROOT_DIR)/../../deps/register_interface/vendor/lowrisc_opentitan/util/regtool.py)
+regtool ?= $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py
 
 RTL := $(patsubst $(ROOT_DIR)/%.hjson,%,$(shell find $(ROOT_DIR) -name "*.hjson"))
 
diff --git a/hardware/src/control_registers/control_registers_reg_pkg.sv b/hardware/src/control_registers/control_registers_reg_pkg.sv
index 0291dc527..c061a7b94 100644
--- a/hardware/src/control_registers/control_registers_reg_pkg.sv
+++ b/hardware/src/control_registers/control_registers_reg_pkg.sv
@@ -1,6 +1,6 @@
-// Copyright 2024 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
 //
 // Register Package auto-generated by `reggen` containing data structure
 
@@ -209,3 +209,4 @@ package control_registers_reg_pkg;
   };
 
 endpackage
+
diff --git a/hardware/src/control_registers/control_registers_reg_top.sv b/hardware/src/control_registers/control_registers_reg_top.sv
index 9258d111d..b089e4c08 100644
--- a/hardware/src/control_registers/control_registers_reg_top.sv
+++ b/hardware/src/control_registers/control_registers_reg_top.sv
@@ -1,6 +1,6 @@
-// Copyright 2024 ETH Zurich and University of Bologna.
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
-// SPDX-License-Identifier: SHL-0.51
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
 //
 // Register Top module auto-generated by `reggen`
 
@@ -993,7 +993,6 @@ module control_registers_reg_top #(
 
 endmodule
 
-/* verilator lint_off DECLFILENAME */
 module control_registers_reg_top_intf
 #(
   parameter int AW = 7,
@@ -1021,12 +1020,12 @@ module control_registers_reg_top_intf
 
   reg_bus_req_t s_reg_req;
   reg_bus_rsp_t s_reg_rsp;
-
+  
   // Assign SV interface to structs
   `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave)
   `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp)
 
-
+  
 
   control_registers_reg_top #(
     .reg_req_t(reg_bus_req_t),
@@ -1041,6 +1040,7 @@ module control_registers_reg_top_intf
     .hw2reg, // Read
     .devmode_i
   );
-
+  
 endmodule
-/* verilator lint_on DECLFILENAME */
+
+
diff --git a/scripts/license-checker.hjson b/scripts/license-checker.hjson
index 8666e0955..b8b3bf88a 100644
--- a/scripts/license-checker.hjson
+++ b/scripts/license-checker.hjson
@@ -21,6 +21,8 @@
     'software/riscv-tests/*'
     'hardware/deps/*'
     'hardware/tb/dpi/elfloader.cpp'
+    'hardware/src/control_registers/control_registers_reg_pkg.sv'
+    'hardware/src/control_registers/control_registers_reg_top.sv'
     'scripts/run_clang_format.py'
     'toolchain/*'
   ]
diff --git a/software/runtime/control_registers.h b/software/runtime/control_registers.h
index f2a467af2..541825143 100644
--- a/software/runtime/control_registers.h
+++ b/software/runtime/control_registers.h
@@ -4,7 +4,7 @@
 // Copyright 2024 ETH Zurich and University of Bologna.
 
 // Licensing information found in source file:
-// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// 
 // SPDX-License-Identifier: SHL-0.51
 
 #ifndef _CONTROL_REGISTERS_REG_DEFS_

From 206fe177178c8658f6584ff908a292565658de10 Mon Sep 17 00:00:00 2001
From: mbertuletti <mbertuletti@iis.ee.ethz.ch>
Date: Wed, 10 Dec 2025 11:10:58 +0100
Subject: [PATCH 12/13] Update Changelog

---
 CHANGELOG.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index b330e4db0..a139a97f3 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -43,6 +43,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 - Add fp8 microkernels: axpy, matmul, batchnorm, layernorm, softmax
 - Optimize fp16 matmul kernel
 - Add fall through register after LSU input
+- Benderize MemPool dependencies
 
 ### Fixed
 - Fix type issue in `snitch_addr_demux`

From 176682c6e4108256c56901e8c0e0d2772e292bad Mon Sep 17 00:00:00 2001
From: mbertuletti <mbertuletti@iis.ee.ethz.ch>
Date: Wed, 10 Dec 2025 11:24:48 +0100
Subject: [PATCH 13/13] Modify README

---
 README.md | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/README.md b/README.md
index bee14d106..003a58779 100644
--- a/README.md
+++ b/README.md
@@ -38,12 +38,6 @@ If the repository path of any submodule changes, run the following command to ch
 git submodule sync --recursive
 ```
 
-MemPool requires to patch a few hardware dependencies. To update the dependencies and apply the patches, run the following command after checking out in the project's root directory:
-
-```bash
-make update-deps
-```
-
 ## Build dependencies
 ### Compiler
 
@@ -64,7 +58,7 @@ make halide
 
 ### RTL Simulation
 
-We use [Bender](https://github.com/pulp-platform/bender) to generate our simulation scripts. Make sure you have Bender installed, or install it in the MemPool repository with:
+We use [Bender](https://github.com/pulp-platform/bender) to checkout hardware dependencies and to generate our simulation scripts. Make sure you have Bender installed, or install it in the MemPool repository with:
 
 ```bash
 # Install Bender