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Herton R. Krzesinski
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Merge: arm64: Update core arch code to v5.19
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/1439 Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2122232 Omitted-fix: 0b52f76 "docs/arm64: elf_hwcaps: unify newlines in HWCAP lists" This is just a documentation whitespace change which we don't need in RHEL. Omitted-fix: c35fe2a elf: Fix the arm64 MTE ELF segment name and value This is a fix for a misnumbered/misnamed ELF segment which isn't actually used in RHEL yet. Update core arm64 code to v5.19 Signed-off-by: Mark Salter <msalter@redhat.com> Approved-by: John W. Linville <linville@redhat.com> Approved-by: Donald Dutile <ddutile@redhat.com> Approved-by: Gavin Shan <gshan@redhat.com> Approved-by: Cornelia Huck <cohuck@redhat.com> Approved-by: Eric Auger <eric.auger@redhat.com> Approved-by: Mark Langsdorf <mlangsdo@redhat.com> Approved-by: David Arcari <darcari@redhat.com> Approved-by: Lenny Szubowicz <lszubowi@redhat.com> Signed-off-by: Herton R. Krzesinski <herton@redhat.com>
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‎Documentation/ABI/testing/sysfs-devices-system-cpu‎

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@@ -493,12 +493,13 @@ What: /sys/devices/system/cpu/cpuX/regs/
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/sys/devices/system/cpu/cpuX/regs/identification/
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/sys/devices/system/cpu/cpuX/regs/identification/midr_el1
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/sys/devices/system/cpu/cpuX/regs/identification/revidr_el1
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/sys/devices/system/cpu/cpuX/regs/identification/smidr_el1
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Date: June 2016
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Contact: Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>
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Description: AArch64 CPU registers
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'identification' directory exposes the CPU ID registers for
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identifying model and revision of the CPU.
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identifying model and revision of the CPU and SMCU.
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What: /sys/devices/system/cpu/aarch32_el0
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Date: May 2021

‎Documentation/arm64/booting.rst‎

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@@ -350,6 +350,16 @@ Before jumping into the kernel, the following conditions must be met:
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- SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
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For CPUs with the Memory Tagging Extension feature (FEAT_MTE2):
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- If EL3 is present:
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- SCR_EL3.ATA (bit 26) must be initialised to 0b1.
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- If the kernel is entered at EL1 and EL2 is present:
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- HCR_EL2.ATA (bit 56) must be initialised to 0b1.
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The requirements described above for CPU mode, caches, MMUs, architected
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timers, coherency and system registers apply to all CPUs. All CPUs must
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enter the kernel in the same exception level. Where the values documented

‎Documentation/arm64/cpu-feature-registers.rst‎

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+------------------------------+---------+---------+
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| RPRES | [7-4] | y |
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+------------------------------+---------+---------+
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| WFXT | [3-0] | y |
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+------------------------------+---------+---------+
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Appendix I: Example

‎Documentation/arm64/elf_hwcaps.rst‎

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Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described
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by Documentation/arm64/memory-tagging-extension.rst.
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HWCAP2_SME
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Functionality implied by ID_AA64PFR1_EL1.SME == 0b0001, as described
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by Documentation/arm64/sme.rst.
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HWCAP2_SME_I16I64
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Functionality implied by ID_AA64SMFR0_EL1.I16I64 == 0b1111.
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HWCAP2_SME_F64F64
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Functionality implied by ID_AA64SMFR0_EL1.F64F64 == 0b1.
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HWCAP2_SME_I8I32
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Functionality implied by ID_AA64SMFR0_EL1.I8I32 == 0b1111.
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HWCAP2_SME_F16F32
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Functionality implied by ID_AA64SMFR0_EL1.F16F32 == 0b1.
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HWCAP2_SME_B16F32
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Functionality implied by ID_AA64SMFR0_EL1.B16F32 == 0b1.
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HWCAP2_SME_F32F32
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Functionality implied by ID_AA64SMFR0_EL1.F32F32 == 0b1.
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HWCAP2_SME_FA64
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Functionality implied by ID_AA64SMFR0_EL1.FA64 == 0b1.
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HWCAP2_WFXT
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Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.
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HWCAP2_EBF16
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Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.
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4. Unused AT_HWCAP bits
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-----------------------
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‎Documentation/arm64/index.rst‎

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perf
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pointer-authentication
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silicon-errata
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sme
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sve
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tagged-address-abi
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tagged-pointers

‎Documentation/arm64/silicon-errata.rst‎

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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A57 | #1319537 | ARM64_ERRATUM_1319367 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A57 | #1742098 | ARM64_ERRATUM_1742098 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A72 | #853709 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A72 | #1319367 | ARM64_ERRATUM_1319367 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A72 | #1655431 | ARM64_ERRATUM_1742098 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_2441009 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |

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