@@ -68,15 +68,13 @@ struct raspberrypi_clk_variant {
6868 char * clkdev ;
6969 unsigned long min_rate ;
7070 bool minimize ;
71- u32 flags ;
7271};
7372
7473static struct raspberrypi_clk_variant
7574raspberrypi_clk_variants [RPI_FIRMWARE_NUM_CLK_ID ] = {
7675 [RPI_FIRMWARE_ARM_CLK_ID ] = {
7776 .export = true,
7877 .clkdev = "cpu0" ,
79- .flags = CLK_IS_CRITICAL ,
8078 },
8179 [RPI_FIRMWARE_CORE_CLK_ID ] = {
8280 .export = true,
@@ -92,12 +90,6 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = {
9290 * always use the minimum the drivers will let us.
9391 */
9492 .minimize = true,
95-
96- /*
97- * It should never be disabled as it drives the bus for
98- * everything else.
99- */
100- .flags = CLK_IS_CRITICAL ,
10193 },
10294 [RPI_FIRMWARE_M2MC_CLK_ID ] = {
10395 .export = true,
@@ -123,15 +115,6 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = {
123115 * drivers will let us.
124116 */
125117 .minimize = true,
126-
127- /*
128- * As mentioned above, this clock is disabled during boot,
129- * the firmware will skip the HSM initialization, resulting
130- * in a bus lockup. Therefore, make sure it's enabled
131- * during boot, but after it, it can be enabled/disabled
132- * by the driver.
133- */
134- .flags = CLK_IGNORE_UNUSED ,
135118 },
136119 [RPI_FIRMWARE_V3D_CLK_ID ] = {
137120 .export = true,
@@ -140,12 +123,10 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = {
140123 [RPI_FIRMWARE_PIXEL_CLK_ID ] = {
141124 .export = true,
142125 .minimize = true,
143- .flags = CLK_IS_CRITICAL ,
144126 },
145127 [RPI_FIRMWARE_HEVC_CLK_ID ] = {
146128 .export = true,
147129 .minimize = true,
148- .flags = CLK_IS_CRITICAL ,
149130 },
150131 [RPI_FIRMWARE_ISP_CLK_ID ] = {
151132 .export = true,
@@ -154,7 +135,6 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = {
154135 [RPI_FIRMWARE_PIXEL_BVB_CLK_ID ] = {
155136 .export = true,
156137 .minimize = true,
157- .flags = CLK_IS_CRITICAL ,
158138 },
159139 [RPI_FIRMWARE_VEC_CLK_ID ] = {
160140 .export = true,
@@ -285,41 +265,7 @@ static int raspberrypi_fw_dumb_determine_rate(struct clk_hw *hw,
285265 return 0 ;
286266}
287267
288- static int raspberrypi_fw_prepare (struct clk_hw * hw )
289- {
290- const struct raspberrypi_clk_data * data = clk_hw_to_data (hw );
291- struct raspberrypi_clk * rpi = data -> rpi ;
292- u32 state = RPI_FIRMWARE_STATE_ENABLE_BIT ;
293- int ret ;
294-
295- ret = raspberrypi_clock_property (rpi -> firmware , data ,
296- RPI_FIRMWARE_SET_CLOCK_STATE , & state );
297- if (ret )
298- dev_err_ratelimited (rpi -> dev ,
299- "Failed to set clock %s state to on: %d\n" ,
300- clk_hw_get_name (hw ), ret );
301-
302- return ret ;
303- }
304-
305- static void raspberrypi_fw_unprepare (struct clk_hw * hw )
306- {
307- const struct raspberrypi_clk_data * data = clk_hw_to_data (hw );
308- struct raspberrypi_clk * rpi = data -> rpi ;
309- u32 state = 0 ;
310- int ret ;
311-
312- ret = raspberrypi_clock_property (rpi -> firmware , data ,
313- RPI_FIRMWARE_SET_CLOCK_STATE , & state );
314- if (ret )
315- dev_err_ratelimited (rpi -> dev ,
316- "Failed to set clock %s state to off: %d\n" ,
317- clk_hw_get_name (hw ), ret );
318- }
319-
320268static const struct clk_ops raspberrypi_firmware_clk_ops = {
321- .prepare = raspberrypi_fw_prepare ,
322- .unprepare = raspberrypi_fw_unprepare ,
323269 .is_prepared = raspberrypi_fw_is_prepared ,
324270 .recalc_rate = raspberrypi_fw_get_rate ,
325271 .determine_rate = raspberrypi_fw_dumb_determine_rate ,
@@ -349,7 +295,7 @@ static struct clk_hw *raspberrypi_clk_register(struct raspberrypi_clk *rpi,
349295 if (!init .name )
350296 return ERR_PTR (- ENOMEM );
351297 init .ops = & raspberrypi_firmware_clk_ops ;
352- init .flags = variant -> flags | CLK_GET_RATE_NOCACHE ;
298+ init .flags = CLK_GET_RATE_NOCACHE ;
353299
354300 data -> hw .init = & init ;
355301
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