@@ -110,7 +110,7 @@ impl Console {
110110 log:: info!( "bmr .................... breakpoint on read memory" ) ;
111111 log:: info!( "bmw .................... breakpoint on write memory" ) ;
112112 log:: info!( "bmx .................... breakpoint on execute memory" ) ;
113- log:: info!( "bcmp ................... break on next cmp or test" ) ;
113+ log:: info!( "bcmp ................... break on next cmp or test instruction " ) ;
114114 log:: info!( "bc ..................... clear breakpoint" ) ;
115115 log:: info!( "n ...................... next instruction" ) ;
116116 log:: info!( "eip .................... change eip" ) ;
@@ -141,8 +141,8 @@ impl Console {
141141 log:: info!( "mdda ................... memory dump all allocations to disk" ) ;
142142 log:: info!( "mt ..................... memory test" ) ;
143143 log:: info!( "r2 [addr] .............. spawn radare2 console if it's isntalled" ) ;
144- log:: info!( "ss ..................... search string" ) ;
145- log:: info!( "sb ..................... search bytes" ) ;
144+ log:: info!( "ss ..................... search string in a specific map " ) ;
145+ log:: info!( "sb ..................... search bytes in a specific map " ) ;
146146 log:: info!( "sba .................... search bytes in all the maps" ) ;
147147 log:: info!( "ssa .................... search string in all the maps" ) ;
148148 log:: info!( "ll ..................... linked list walk" ) ;
@@ -178,20 +178,29 @@ impl Console {
178178 let base = format ! ( "0x{:x}" , mem. get_base( ) ) ;
179179 let seek = format ! ( "0x{:x}" , addr) ;
180180 let bits;
181+ let precmd: String ;
181182 if emu. cfg . is_64bits {
182- bits = "64"
183+ bits = "64" ;
184+ precmd = format ! (
185+ "dr rax={}; dr rbx={}; dr rcx={}; dr rdx={}; dr rsi={};
186+ dr rdi={}; dr rbp={}; dr rsp={}; dr rip={}; dr r8={}
187+ dr r9={}; dr r10={}; dr r11={}; dr r12={}; dr r13={};
188+ dr r14={}; dr r15={}; decai -e model=qwen3-coder:30b; r2ai -e r2ai.model=qwen3-coder:30b;" ,
189+ emu. regs( ) . rax, emu. regs( ) . rbx, emu. regs( ) . rcx, emu. regs( ) . rdx,
190+ emu. regs( ) . rsi, emu. regs( ) . rdi, emu. regs( ) . rbp, emu. regs( ) . rsp,
191+ emu. regs( ) . rip, emu. regs( ) . r8, emu. regs( ) . r9, emu. regs( ) . r10,
192+ emu. regs( ) . r11, emu. regs( ) . r12, emu. regs( ) . r13, emu. regs( ) . r14,
193+ emu. regs( ) . r15) ;
183194 } else {
184- bits = "32"
195+ bits = "32" ;
196+ precmd = format ! (
197+ "dr eax={}; dr ebx={}; dr ecx={}; dr edx={}; dr esi={}; \
198+ dr edi={}; dr ebp={}; dr esp={}; dr eip={}; \
199+ decai -e model=qwen3-coder:30b; r2ai -e r2ai.model=qwen3-coder:30b;",
200+ emu. regs( ) . get_eax( ) , emu. regs( ) . get_ebx( ) , emu. regs( ) . get_ecx( ) , emu. regs( ) . get_edx( ) ,
201+ emu. regs( ) . get_esi( ) , emu. regs( ) . get_edi( ) , emu. regs( ) . get_ebp( ) , emu. regs( ) . get_esp( ) ,
202+ emu. regs( ) . get_eip( ) ) ;
185203 }
186- let precmd = format ! ( "dr rax={}?; dr rbx={}?; dr rcx={}?; dr rdx={}?; dr rsi={}?;
187- dr rdi={}?; dr rbp={}?; dr rsp={}?; dr rip={}?; dr r8={}?
188- dr r9={}?; dr r10={}?; dr r11={}?; dr r12={}?; dr r13={}?;
189- dr r14={}?; dr r15={}?; decai -e model=qwen3-coder:30b; r2ai -e r2ai.model=qwen3-coder:30b;" ,
190- emu. regs( ) . rax, emu. regs( ) . rbx, emu. regs( ) . rcx, emu. regs( ) . rdx,
191- emu. regs( ) . rsi, emu. regs( ) . rdi, emu. regs( ) . rbp, emu. regs( ) . rsp,
192- emu. regs( ) . rip, emu. regs( ) . r8, emu. regs( ) . r9, emu. regs( ) . r10,
193- emu. regs( ) . r11, emu. regs( ) . r12, emu. regs( ) . r13, emu. regs( ) . r14,
194- emu. regs( ) . r15) ;
195204 let r2args = vec ! [
196205 "-n" , "-a" , "x86" , "-b" , & bits, "-m" , & base, "-s" , & seek, "-c" , & precmd, & tmpfile,
197206 ] ;
@@ -486,6 +495,7 @@ impl Console {
486495 log:: info!( "pos = 0x{:x}" , emu. pos) ;
487496 }
488497 "c" => {
498+ emu. exp += 1 ;
489499 emu. is_running . store ( 1 , atomic:: Ordering :: Relaxed ) ;
490500 return ;
491501 }
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