From 17e586f3bdc2770a413f827f4e0f1576a4629246 Mon Sep 17 00:00:00 2001 From: Sujeev Dias Date: Thu, 25 Jul 2019 15:14:52 -0700 Subject: [PATCH 01/15] mhi: core: wakeup waiters if early error is received The esoc framework notifies MHI of a device assert using early hooks. As part of moving MHI to an error state, wake up any waiting threads so they can bail out early. CRs-Fixed: 2500104 Change-Id: I8bf9b085cef078f0692ad198ca1ba2a8149c3172 Acked-by: Bhaumik Vasav Bhatt Signed-off-by: Sujeev Dias --- drivers/bus/mhi/core/mhi_pm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/bus/mhi/core/mhi_pm.c b/drivers/bus/mhi/core/mhi_pm.c index 190d0ffad3003..41b79d20b1c3e 100644 --- a/drivers/bus/mhi/core/mhi_pm.c +++ b/drivers/bus/mhi/core/mhi_pm.c @@ -873,6 +873,9 @@ void mhi_control_error(struct mhi_controller *mhi_cntrl) goto exit_control_error; } + /* notify waiters to bail out early since MHI has entered ERROR state */ + wake_up_all(&mhi_cntrl->state_event); + /* start notifying all clients who request early notification */ device_for_each_child(mhi_cntrl->dev, NULL, mhi_early_notify_device); From 5f98983fc1a73d1127e4cd6c82b1daaa278ded58 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 1 Aug 2019 19:35:29 -0700 Subject: [PATCH 02/15] pci: framework: skip PCI restore in pci_pm_resume if no_d3hot is set PCI devices with no_d3hot set do not need its configuration space restored in pci_pm_resume. Change-Id: Ia92f5278bfbd35d082fce53d9b2de9397a69b942 Signed-off-by: Tony Truong --- drivers/pci/pci-driver.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 4f95fe8f25c40..f330ae77bfbea 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -855,6 +855,9 @@ static int pci_pm_resume(struct device *dev) const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL; int error = 0; + if (pci_dev->no_d3hot) + goto skip_pci_pm_restore; + /* * This is necessary for the suspend error path in which resume is * called without restoring the standard config registers of the device. @@ -862,6 +865,7 @@ static int pci_pm_resume(struct device *dev) if (pci_dev->state_saved) pci_restore_standard_config(pci_dev); +skip_pci_pm_restore: if (pci_has_legacy_pm_support(pci_dev)) return pci_legacy_resume(dev); From cee46aeefffbe9415cfd593ee1ce125875f3e4ea Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Mon, 12 Aug 2019 14:35:32 -0700 Subject: [PATCH 03/15] f_fs: Return correct USB endpoint descriptor to user space daemon Some of user space daemon like ADB queries endpoint descriptor using ioctl to know wMaxPacketSize value. Based on wMaxPacketSize value it queues additional buffer to read zero length packet if expected read buffer size is multiple of wMaxPacketSize. Currently driver is missing handling for super speed plus case which results into sending full speed related USB endpoint descriptor (i.e. wMaxPacketSize 64 bytes). Hence when adbd is expecting 64 bytes packet from host, it queues one more additional buffer. This results into mismatch of ADB command and response when multiple ADB commands are used and causing different ADB related stability issues. Fix this issue adding super speed plus check with FUNCTIONFS_ENDPOINT_DESC ioctl command. Change-Id: I9416295c07c2d98f9d32df43d7e506f975da15a2 Signed-off-by: Mayank Rana --- drivers/usb/gadget/function/f_fs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index c603392fd1bf6..f32233bd58225 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -1401,6 +1401,7 @@ static long ffs_epfile_ioctl(struct file *file, unsigned code, struct usb_endpoint_descriptor desc1, *desc; switch (epfile->ffs->gadget->speed) { + case USB_SPEED_SUPER_PLUS: case USB_SPEED_SUPER: desc_idx = 2; break; From 547480c5c3823dab843d95bbfb63bd6b4d5e5dc2 Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Wed, 24 Jul 2019 15:01:20 +0530 Subject: [PATCH 04/15] usb: phy: snps: Turn off CXO clock from msm_hsphy_dpdm_regulator_enable dpdm_regulator_enable() function turn on the CXO clk to program the phy registers to put PHY in non-driving mode for charger detection. In charger connected case phy driver voting for CXO clock in dpdm_regulator_enable but does not disabling it which is preventing the system from vdd minimization. Hence fix this issue by turning off the CXO clk from dpdm_regulator_enable. Change-Id: Ib3a04eedcef625443077199d5920884f114db82d Signed-off-by: Chandana Kishori Chiluveru --- drivers/usb/phy/phy-msm-snps-hs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/phy/phy-msm-snps-hs.c b/drivers/usb/phy/phy-msm-snps-hs.c index 196d46eda0458..89d6a8e64cc42 100644 --- a/drivers/usb/phy/phy-msm-snps-hs.c +++ b/drivers/usb/phy/phy-msm-snps-hs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -578,6 +578,7 @@ static int msm_hsphy_dpdm_regulator_enable(struct regulator_dev *rdev) UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN, UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN); + msm_hsphy_enable_clocks(phy, false); phy->dpdm_enable = true; } mutex_unlock(&phy->phy_lock); @@ -596,7 +597,6 @@ static int msm_hsphy_dpdm_regulator_disable(struct regulator_dev *rdev) mutex_lock(&phy->phy_lock); if (phy->dpdm_enable) { if (!phy->cable_connected) { - msm_hsphy_enable_clocks(phy, false); ret = msm_hsphy_enable_power(phy, false); if (ret < 0) { mutex_unlock(&phy->phy_lock); From faadeea364051db3e5392835fb020d66ad4d9ba5 Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Wed, 6 Jun 2018 19:54:17 +0530 Subject: [PATCH 05/15] mmc: core: Update SD card removal logic based on cd gpio state Update SD card removal event processing logic. Instead of pinging the card to know the card presence rely on card-detect gpio state. On multi-card tray designs, the same card-tray would be used for SD card and SIM cards. If SD card is placed at the rightmost location in the tray, then SIM card may come in contact with SD card power- supply while removing the tray. It may result in SIM damage. For protecting SIM from this issue, in multi-card tray designs, a h/w fix done such that pmic gets a notification of SD card removal event (through hardwiring) and it turns off the SD card voltage regulators immediately. All this will be done much before SD card driver starts processing card removal event. To support this design, SD card driver shouldn't turn-on the regulator while processing card removal event. But the present mmc driver turns-on regulator (multiple times if the card was in suspend state). To avoid turning on SD card regulator in card removal path, updating the card removal processing logic is based on card detect gpio state. Change-Id: I13708a60c9378519713ebec8071ae3b130012a93 Signed-off-by: Veerabhadrarao Badiganti Signed-off-by: Sarthak Garg --- drivers/mmc/core/block.c | 4 ---- drivers/mmc/core/core.c | 20 +++++++++++++------- drivers/mmc/core/sd.c | 22 ++++++++++++++++++++++ drivers/mmc/core/slot-gpio.c | 4 ++++ include/linux/mmc/host.h | 6 ++++++ 5 files changed, 45 insertions(+), 11 deletions(-) diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c index 271073205b544..f4a5d4f28ee2a 100644 --- a/drivers/mmc/core/block.c +++ b/drivers/mmc/core/block.c @@ -4297,9 +4297,7 @@ static int mmc_blk_probe(struct mmc_card *card) dev_set_drvdata(&card->dev, md); -#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME mmc_set_bus_resume_policy(card->host, 1); -#endif if (mmc_add_disk(md)) goto out; @@ -4353,9 +4351,7 @@ static void mmc_blk_remove(struct mmc_card *card) pm_runtime_put_noidle(&card->dev); mmc_blk_remove_req(md); dev_set_drvdata(&card->dev, NULL); -#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME mmc_set_bus_resume_policy(card->host, 0); -#endif } static int _mmc_blk_suspend(struct mmc_card *card, bool wait) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index e2f7a10f468bb..2499c22629741 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -1978,10 +1978,9 @@ EXPORT_SYMBOL(mmc_start_areq); */ void mmc_wait_for_req(struct mmc_host *host, struct mmc_request *mrq) { -#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME if (mmc_bus_needs_resume(host)) mmc_resume_bus(host); -#endif + __mmc_start_req(host, mrq); if (!mrq->cap_cmd_during_tfr) @@ -2293,10 +2292,9 @@ void mmc_get_card(struct mmc_card *card) { pm_runtime_get_sync(&card->dev); mmc_claim_host(card->host); -#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME + if (mmc_bus_needs_resume(card->host)) mmc_resume_bus(card->host); -#endif } EXPORT_SYMBOL(mmc_get_card); @@ -3252,6 +3250,7 @@ int mmc_resume_bus(struct mmc_host *host) { unsigned long flags; int err = 0; + int card_present = true; if (!mmc_bus_needs_resume(host)) return -EINVAL; @@ -3262,7 +3261,10 @@ int mmc_resume_bus(struct mmc_host *host) spin_unlock_irqrestore(&host->lock, flags); mmc_bus_get(host); - if (host->bus_ops && !host->bus_dead && host->card) { + if (host->ops->get_cd) + card_present = host->ops->get_cd(host); + + if (host->bus_ops && !host->bus_dead && host->card && card_present) { mmc_power_up(host, host->card->ocr); BUG_ON(!host->bus_ops->resume); err = host->bus_ops->resume(host); @@ -4584,7 +4586,7 @@ static int mmc_pm_notify(struct notifier_block *notify_block, struct mmc_host *host = container_of( notify_block, struct mmc_host, pm_notify); unsigned long flags; - int err = 0; + int err = 0, present = 0; switch (mode) { case PM_HIBERNATION_PREPARE: @@ -4627,8 +4629,12 @@ static int mmc_pm_notify(struct notifier_block *notify_block, spin_lock_irqsave(&host->lock, flags); host->rescan_disable = 0; + if (host->ops->get_cd) + present = host->ops->get_cd(host); + if (mmc_bus_manual_resume(host) && - !host->ignore_bus_resume_flags) { + !host->ignore_bus_resume_flags && + present) { spin_unlock_irqrestore(&host->lock, flags); break; } diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 1582e4ab6da54..9388bf7dc439b 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -1156,6 +1156,9 @@ static void mmc_sd_remove(struct mmc_host *host) */ static int mmc_sd_alive(struct mmc_host *host) { + if (host->ops->get_cd && !host->ops->get_cd(host)) + return -ENOMEDIUM; + return mmc_send_status(host->card, NULL); } @@ -1181,6 +1184,16 @@ static void mmc_sd_detect(struct mmc_host *host) return; } + if (mmc_bus_needs_resume(host)) + mmc_resume_bus(host); + + if (host->ops->get_cd && !host->ops->get_cd(host)) { + err = -ENOMEDIUM; + mmc_card_set_removed(host->card); + mmc_card_clr_suspended(host->card); + goto out; + } + /* * Just check if our card has been removed. */ @@ -1203,6 +1216,7 @@ static void mmc_sd_detect(struct mmc_host *host) err = _mmc_detect_card_removed(host); #endif +out: mmc_put_card(host->card); if (err) { @@ -1281,6 +1295,11 @@ static int _mmc_sd_resume(struct mmc_host *host) if (!mmc_card_suspended(host->card)) goto out; + if (host->ops->get_cd && !host->ops->get_cd(host)) { + mmc_card_clr_suspended(host->card); + goto out; + } + mmc_power_up(host, host->card->ocr); #ifdef CONFIG_MMC_PARANOID_SD_INIT retries = 5; @@ -1376,6 +1395,9 @@ static int mmc_sd_runtime_resume(struct mmc_host *host) static int mmc_sd_reset(struct mmc_host *host) { + if (host->ops->get_cd && !host->ops->get_cd(host)) + return -ENOMEDIUM; + mmc_power_cycle(host, host->card->ocr); return mmc_sd_init_card(host, host->card->ocr, host->card); } diff --git a/drivers/mmc/core/slot-gpio.c b/drivers/mmc/core/slot-gpio.c index 446334ba6e173..c3d8fd250423d 100644 --- a/drivers/mmc/core/slot-gpio.c +++ b/drivers/mmc/core/slot-gpio.c @@ -54,6 +54,10 @@ static irqreturn_t mmc_gpio_cd_irqt(int irq, void *dev_id) struct mmc_host *host = dev_id; struct mmc_gpio *ctx = host->slot.handler_priv; int status; + int present = host->ops->get_cd(host); + + pr_debug("%s: cd gpio irq, gpio state %d (CARD_%s)\n", + mmc_hostname(host), present, present?"INSERT":"REMOVAL"); if (!host->ops) goto out; diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index b207dd16b120f..671842fcfaa92 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -763,6 +763,7 @@ static inline void *mmc_cmdq_private(struct mmc_host *host) #define mmc_bus_manual_resume(host) ((host)->bus_resume_flags & \ MMC_BUSRESUME_MANUAL_RESUME) +#ifdef CONFIG_MMC_BLOCK_DEFERRED_RESUME static inline void mmc_set_bus_resume_policy(struct mmc_host *host, int manual) { if (manual) @@ -770,6 +771,11 @@ static inline void mmc_set_bus_resume_policy(struct mmc_host *host, int manual) else host->bus_resume_flags &= ~MMC_BUSRESUME_MANUAL_RESUME; } +#else +static inline void mmc_set_bus_resume_policy(struct mmc_host *host, int manual) +{ +} +#endif extern int mmc_resume_bus(struct mmc_host *host); From f2ac283e21205c561a80c0bbe84876ffeadf044a Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Fri, 12 Jul 2019 18:35:35 +0530 Subject: [PATCH 06/15] Revert "mmc: core: rescan for card if deferred resume fails" This reverts commit 9de18caa8e7d40afc3585822bdec785c0ae32e33. Reverting this change as this is introducing race condition with sdcard plug out scenario and leading to device crash. 1. Deferred resume kicks in 2. SDCard is plugged out 3. Deferred resume failed 4. SDCard detection scheduled as resume fails 5. Device crashing Change-Id: I6fd81d6c21be4a0e3139246c9d66959010fd240c Signed-off-by: Ram Prakash Gupta Signed-off-by: Sarthak Garg --- drivers/mmc/core/core.c | 17 +---------------- drivers/mmc/core/sd.c | 2 -- 2 files changed, 1 insertion(+), 18 deletions(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 2499c22629741..916b30caf235a 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -3267,22 +3267,7 @@ int mmc_resume_bus(struct mmc_host *host) if (host->bus_ops && !host->bus_dead && host->card && card_present) { mmc_power_up(host, host->card->ocr); BUG_ON(!host->bus_ops->resume); - err = host->bus_ops->resume(host); - if (err) { - pr_err("%s: %s: resume failed: %d\n", - mmc_hostname(host), __func__, err); - /* - * If we have cd-gpio based detection mechanism and - * deferred resume is supported, we will not detect - * card removal event when system is suspended. So if - * resume fails after a system suspend/resume, - * schedule the work to detect card presence. - */ - if (mmc_card_is_removable(host) && - !(host->caps & MMC_CAP_NEEDS_POLL)) { - mmc_detect_change(host, 0); - } - } + host->bus_ops->resume(host); if (mmc_card_cmdq(host->card)) { err = mmc_cmdq_halt(host, false); if (err) diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 9388bf7dc439b..2ecc943762fa4 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -1326,8 +1326,6 @@ static int _mmc_sd_resume(struct mmc_host *host) mmc_hostname(host), __func__, err); mmc_card_set_removed(host->card); mmc_detect_change(host, msecs_to_jiffies(200)); - } else if (err) { - goto out; } mmc_card_clr_suspended(host->card); From d91856cc95cf44173fdac59f6b6e3b37dac26f0a Mon Sep 17 00:00:00 2001 From: Asutosh Das Date: Tue, 2 Jan 2018 15:38:27 +0530 Subject: [PATCH 07/15] mmc: core: Reset on error during deferred resume If resume fails, there is no way to handle it now. Also there's no attempt to recover from it. This leads to lot of warnings while issuing requests. Check for resume errors & reset the stack on error as an attempt to recover from it. Change-Id: Ie4d6d2a34c2c7a8154696e93d85e50d60410e0c2 Signed-off-by: Asutosh Das Signed-off-by: Ram Prakash Gupta Signed-off-by: Sarthak Garg --- drivers/mmc/core/core.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 916b30caf235a..6da3d5fda3d07 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -3267,20 +3267,31 @@ int mmc_resume_bus(struct mmc_host *host) if (host->bus_ops && !host->bus_dead && host->card && card_present) { mmc_power_up(host, host->card->ocr); BUG_ON(!host->bus_ops->resume); - host->bus_ops->resume(host); + err = host->bus_ops->resume(host); + if (err && (err != -ENOMEDIUM)) { + pr_err("%s: bus resume: failed: %d\n", + mmc_hostname(host), err); + err = mmc_hw_reset(host); + if (err) { + pr_err("%s: reset: failed: %d\n", + mmc_hostname(host), err); + goto err_reset; + } else { + mmc_card_clr_suspended(host->card); + } + } if (mmc_card_cmdq(host->card)) { err = mmc_cmdq_halt(host, false); if (err) pr_err("%s: %s: unhalt failed: %d\n", mmc_hostname(host), __func__, err); - else - mmc_card_clr_suspended(host->card); } } +err_reset: mmc_bus_put(host); pr_debug("%s: Deferred resume completed\n", mmc_hostname(host)); - return 0; + return err; } EXPORT_SYMBOL(mmc_resume_bus); From cb03373d7e141a31d283da43bffb2d18efd44aad Mon Sep 17 00:00:00 2001 From: Asutosh Das Date: Wed, 3 Apr 2019 16:35:33 +0530 Subject: [PATCH 08/15] mmc: sd: set card removed to true Sometimes when the card is removed and a request is in queue the resume fails. But there's no way to inform the in-flight request that the card is removed since the resume itself fails and rescan is waiting for claim_host which was acquired by the in-flight request. This request percolates to platform driver which sees that the pre-requisites to issue the request are not met i.e. the clocks are OFF. So it tries to dump the registers and results in a NoC error. Set the card removed when resume fails to avoid this problem. CRs-fixed: 2430862 Change-Id: I171ad435ec11c1212e6528592b8db43cd0171b11 Signed-off-by: Asutosh Das Signed-off-by: Ram Prakash Gupta Signed-off-by: Sarthak Garg --- drivers/mmc/core/core.c | 9 ++++++++- drivers/mmc/core/sd.c | 18 ++++++++++++++---- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 6da3d5fda3d07..19b2c87fa8005 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -3261,8 +3261,15 @@ int mmc_resume_bus(struct mmc_host *host) spin_unlock_irqrestore(&host->lock, flags); mmc_bus_get(host); - if (host->ops->get_cd) + if (host->ops->get_cd) { card_present = host->ops->get_cd(host); + if (!card_present) { + pr_err("%s: Card removed - card_present:%d\n", + mmc_hostname(host), card_present); + mmc_card_set_removed(host->card); + } + } + if (host->bus_ops && !host->bus_dead && host->card && card_present) { mmc_power_up(host, host->card->ocr); diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 2ecc943762fa4..4dd4eb1e034ce 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -1350,11 +1350,21 @@ static int mmc_sd_resume(struct mmc_host *host) MMC_TRACE(host, "%s: Enter\n", __func__); err = _mmc_sd_resume(host); - pm_runtime_set_active(&host->card->dev); - pm_runtime_mark_last_busy(&host->card->dev); - pm_runtime_enable(&host->card->dev); - MMC_TRACE(host, "%s: Exit err: %d\n", __func__, err); + if (err) { + pr_err("%s: sd resume err: %d\n", mmc_hostname(host), err); + if (host->ops->get_cd && !host->ops->get_cd(host)) { + err = -ENOMEDIUM; + mmc_card_set_removed(host->card); + } + } + if (err != -ENOMEDIUM) { + pm_runtime_set_active(&host->card->dev); + pm_runtime_mark_last_busy(&host->card->dev); + pm_runtime_enable(&host->card->dev); + } + + MMC_TRACE(host, "%s: Exit err: %d\n", __func__, err); return err; } From 4343da0ceb1b0f1029617b063caff25382527d55 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Stefan=20R=C3=BCcker?= Date: Sat, 1 Aug 2020 10:50:15 +0200 Subject: [PATCH 09/15] msm: vidc: Remove extraneous register read in power off MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The read was introduced with commit ID: 8e8bb1a9ad0622009f6b719fcc7f43082febc738 and it is a leftover from cherry picking the commit with the ID: e8c6f4c97b1fe1a53951741e497dfd18bb1e607b. Signed-off-by: Stefan Rücker --- drivers/media/platform/msm/vidc/venus_hfi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/media/platform/msm/vidc/venus_hfi.c b/drivers/media/platform/msm/vidc/venus_hfi.c index def431d49dfb0..103eb1f685804 100644 --- a/drivers/media/platform/msm/vidc/venus_hfi.c +++ b/drivers/media/platform/msm/vidc/venus_hfi.c @@ -4774,8 +4774,6 @@ static void __venus_power_off(struct venus_hfi_device *device, bool axi_reset) disable_irq_nosync(device->hal_data->irq); device->intr_status = 0; - version = __read_register(device, VIDC_WRAPPER_HW_VERSION); - if (axi_reset) version = __read_register(device, VIDC_WRAPPER_HW_VERSION); From 7fbb163042a21bd3d3420b6531e1eac631274596 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Thu, 18 Jul 2019 20:12:30 +0530 Subject: [PATCH 10/15] ARM: dts: msm: Add dtsi support for v150_110 camera Camera CAMNOC, ICP, IPE, BPS, CDM, SMMU, JPEG, IFE, PPI nodes are added for chipsets having v150_110 camera. Change-Id: Iea631ba2f7a48fa1a144769097acdc865cfbbbdc Signed-off-by: Chandan Kumar Jha --- .../bindings/media/video/msm-cam-ppi.txt | 102 ++ arch/arm64/boot/dts/qcom/atoll-camera.dtsi | 869 ++++++++++++++++++ 2 files changed, 971 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/video/msm-cam-ppi.txt create mode 100644 arch/arm64/boot/dts/qcom/atoll-camera.dtsi diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-ppi.txt b/Documentation/devicetree/bindings/media/video/msm-cam-ppi.txt new file mode 100644 index 0000000000000..aeed60fa6055f --- /dev/null +++ b/Documentation/devicetree/bindings/media/video/msm-cam-ppi.txt @@ -0,0 +1,102 @@ +* Qualcomm Technologies, Inc. MSM camera PPI + +======================= +Required Node Structure +======================= +The camera PPI node must be described in First level of device nodes. The +first level describe the overall PPI node structure. + +====================================== +First Level Node - PPI device +====================================== + +- compatible + Usage: required + Value type: + Definition: Should be "qcom,ppi-v1.0", + "qcom,ppi-v1.1", "qcom,ppi-v1.2", + "qcom,ppi-v2.0", "qcom,ppi". + +- cell-index: ppi hardware core index + Usage: required + Value type: + Definition: Should specify the Hardware index id. + +- reg + Usage: required + Value type: + Definition: offset and length of the register set + for the device for the ppi operating in + compatible mode. + +- reg-names + Usage: required + Value type: + Definition: Should specify relevant names to each + reg property defined. + +- reg-cam-base + Usage: required + Value type: + Definition: offset of PPI in camera hw block + +- interrupts + Usage: required + Value type: + Definition: Interrupt associated with PPI HW. + +- interrupt-names + Usage: required + Value type: + Definition: Name of the interrupt. + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for PPI HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clock rates in Hz for PPI HW. + +- clock-cntl-level + Usage: required + Value type: + Definition: All different clock level node can support. + +- clocks + Usage: required + Value type: + Definition: all clock phandle and source clocks. + +- regulator-names + Usage: required + Value type: + Definition: name of the voltage regulators required for the device. + +- gdscr-supply + Usage: required + Value type: + Definition: should contain gdsr regulator used for PPI clocks. + +Example: + qcom,ppi0@ace0000 { + cell-index = <0>; + compatible = "qcom,ppi170"; + reg-names = "ppi"; + reg = <0xace0000 0x200>; + reg-cam-base = <0xe0000>; + interrupt-names = "ppi"; + interrupts = <0 202 0>; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_PPI0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", "ppi0_clk" + clock-rates = <400000000 0 300000000 0>; + clock-cntl-level = "turbo"; + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-camera.dtsi b/arch/arm64/boot/dts/qcom/atoll-camera.dtsi new file mode 100644 index 0000000000000..05665defb5b28 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/atoll-camera.dtsi @@ -0,0 +1,869 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x820 0x0>, + <&apps_smmu 0x840 0x0>, + <&apps_smmu 0x860 0x0>; + label = "ife"; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_lrme { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0cc0 0x0>, + <&apps_smmu 0x0d40 0x0>; + label = "lrme"; + lrme_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 100MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + /* IO region is approximately 3.3 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0xd800000>; + iova-region-len = <0xd2800000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xd80 0x20>, + <&apps_smmu 0xda0 0x20>; + label = "jpeg"; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0ce2 0x0>, + <&apps_smmu 0x0c80 0x0>, + <&apps_smmu 0x0ca0 0x0>, + <&apps_smmu 0x0d00 0x0>, + <&apps_smmu 0x0d20 0x0>; + label = "icp"; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x1>; + iova-granularity = <0x15>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10A00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3 GB */ + iova-region-name = "io"; + iova-region-start = <0x10B11000>; + iova-region-len = <0xCF4EF000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* qdss region is approximately 64K */ + iova-region-name = "qdss"; + iova-region-start = <0x10B00000>; + iova-region-len = <0x10000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x0d60 0x0>, + <&apps_smmu 0x0d61 0x0>; + label = "cpas-cdm0"; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-cpas@ac40000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0xac40000 0x1000>, + <0xac42000 0x5000>; + reg-cam-base = <0x40000 0x42000>; + interrupt-names = "cpas_camnoc"; + interrupts = <0 459 0>; + qcom,cpas-hw-ver = <0x150110>; /* Titan v150 v1.1.0 */ + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = "gcc_ahb_clk", + "gcc_axi_clk", + "soc_ahb_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "camnoc_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; + src-clock-name = "slow_ahb_clk_src"; + clock-rates = <0 0 0 0 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>; + clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + //qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "suspend", + "minsvs", "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "csid0", "csid1", "csid2", "cci0", + "ife0", "ife1", "ife2", "ipe0", + "ipe1", "cam-cdm-intf0", "cpas-cdm0", "bps0", + "icp0", "jpeg-dma0", "jpeg-enc0", "lrmecpas0"; + client-axi-port-names = + "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_hf_2", + "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", + "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", + "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", + "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1"; + client-bus-camnoc-based; + qcom,axi-port-list { + qcom,axi-port1 { + qcom,axi-port-name = "cam_hf_1"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_hf_1_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_hf_1_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + qcom,axi-port2 { + qcom,axi-port-name = "cam_hf_2"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_hf_2_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_hf_2_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + qcom,axi-port3 { + qcom,axi-port-name = "cam_sf_1"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = "cam_sf_1_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + qcom,axi-port-camnoc { + qcom,msm-bus,name = "cam_sf_1_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + }; + + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,a5", + "qcom,ipe0", + "qcom,bps"; + num-a5 = <1>; + num-ipe = <1>; + num-bps = <1>; + icp_pc_en; + status = "ok"; + }; + + cam_a5: qcom,a5@ac00000 { + cell-index = <0>; + compatible = "qcom,cam-a5"; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "a5_qgic", "a5_sierra", "a5_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = <0 463 0>; + interrupt-names = "a5"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = "gcc_cam_ahb_clk", + "gcc_cam_axi_clk", + "soc_fast_ahb", + "soc_ahb_clk", + "cpas_ahb_clk", + "camnoc_axi_clk", + "icp_clk", + "icp_clk_src"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_ICP_CLK>, + <&clock_camcc CAM_CC_ICP_CLK_SRC>; + + clock-rates = + <0 0 200000000 0 0 0 0 360000000>, + <0 0 200000000 0 0 0 0 600000000>; + clock-cntl-level = "svs", "turbo"; + fw_name = "CAMERA_ICP.elf"; + ubwc-cfg = <0x73 0x1CF>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac87000 0x3000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x87000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&ipe_0_gdsc>; + clock-names = "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk", + "ipe_0_clk_src"; + src-clock-name = "ipe_0_clk_src"; + clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_0_AREG_CLK>, + <&clock_camcc CAM_CC_IPE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IPE_0_CLK>, + <&clock_camcc CAM_CC_IPE_0_CLK_SRC>; + + clock-rates = + <0 0 0 0 360000000>, + <0 0 0 0 432000000>, + <0 0 0 0 540000000>, + <0 0 0 0 600000000>; + clock-cntl-level = "svs", + "svs_l1", "nominal", "turbo"; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac6f000 0x3000>; + reg-names = "bps_top"; + reg-cam-base = <0x6f000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&bps_gdsc>; + clock-names = "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk", + "bps_clk_src"; + src-clock-name = "bps_clk_src"; + clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>, + <&clock_camcc CAM_CC_BPS_AREG_CLK>, + <&clock_camcc CAM_CC_BPS_AXI_CLK>, + <&clock_camcc CAM_CC_BPS_CLK>, + <&clock_camcc CAM_CC_BPS_CLK_SRC>; + + clock-rates = + <0 0 0 0 360000000>, + <0 0 0 0 432000000>, + <0 0 0 0 480000000>, + <0 0 0 0 600000000>; + clock-cntl-level = "svs", + "svs_l1", "nominal", "turbo"; + status = "ok"; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc", + "lrmecdm"; + status = "ok"; + }; + + qcom,cpas-cdm0@ac48000 { + cell-index = <0>; + compatible = "qcom,cam170-cpas-cdm0"; + label = "cpas-cdm"; + reg = <0xac48000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x48000>; + interrupts = <0 469 0>; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "gcc_camera_ahb", + "gcc_camera_axi", + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_camnoc_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-rates = <0 0 0 0 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb3000 { + cell-index = <0>; + compatible = "qcom,csid170"; + reg-names = "csid"; + reg = <0xacb3000 0x1000>; + reg-cam-base = <0xb3000>; + interrupt-names = "csid"; + interrupts = <0 464 0>; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "ife_csid_clk", + "ife_csid_clk_src", + "ife_cphy_rx_clk", + "cphy_rx_clk_src", + "ife_clk", + "ife_clk_src", + "camnoc_axi_clk", + "ife_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 270000000 0 0 0 360000000 0 0>, + <0 0 0 0 0 0 480000000 0 0 0 600000000 0 0>; + clock-cntl-level = "svs", "turbo"; + src-clock-name = "ife_csid_clk_src"; + ppi-enable; + status = "ok"; + }; + + cam_vfe0: qcom,vfe0@acaf000 { + cell-index = <0>; + compatible = "qcom,vfe170"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacaf000 0x4000>, + <0xac42000 0x5000>; + reg-cam-base = <0xaf000 0x42000>; + interrupt-names = "ife"; + interrupts = <0 465 0>; + regulator-names = "camss", "ife0"; + camss-supply = <&titan_top_gdsc>; + ife0-supply = <&ife_0_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "ife_clk", + "ife_clk_src", + "camnoc_axi_clk", + "ife_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 360000000 0 0>, + <0 0 0 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 600000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <600000000>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acba000 { + cell-index = <1>; + compatible = "qcom,csid170"; + reg-names = "csid"; + reg = <0xacba000 0x1000>; + reg-cam-base = <0xba000>; + interrupt-names = "csid"; + interrupts = <0 466 0>; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "ife_csid_clk", + "ife_csid_clk_src", + "ife_cphy_rx_clk", + "cphy_rx_clk_src", + "ife_clk", + "ife_clk_src", + "camnoc_axi_clk", + "ife_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 270000000 0 0 0 360000000 0 0>, + <0 0 0 0 0 0 480000000 0 0 0 600000000 0 0>; + clock-cntl-level = "svs", "turbo"; + src-clock-name = "ife_csid_clk_src"; + ppi-enable; + status = "ok"; + }; + + cam_vfe1: qcom,vfe1@acb6000 { + cell-index = <1>; + compatible = "qcom,vfe170"; + reg-names = "ife", "cam_camnoc"; + reg = <0xacb6000 0x4000>, + <0xac42000 0x5000>; + reg-cam-base = <0xb6000 0x42000>; + interrupt-names = "ife"; + interrupts = <0 467 0>; + regulator-names = "camss", "ife1"; + camss-supply = <&titan_top_gdsc>; + ife1-supply = <&ife_1_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "ife_clk", + "ife_clk_src", + "camnoc_axi_clk", + "ife_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 360000000 0 0>, + <0 0 0 0 0 0 432000000 0 0>, + <0 0 0 0 0 0 600000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <600000000>; + status = "ok"; + }; + + cam_csid_lite: qcom,csid-lite@acc8000 { + cell-index = <2>; + compatible = "qcom,csid-lite170"; + reg-names = "csid-lite"; + reg = <0xacc8000 0x1000>; + reg-cam-base = <0xc8000>; + interrupt-names = "csid-lite"; + interrupts = <0 473 0>; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "ife_csid_clk", + "ife_csid_clk_src", + "ife_cphy_rx_clk", + "cphy_rx_clk_src", + "ife_clk", + "ife_clk_src", + "camnoc_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 270000000 0 0 0 360000000 0>, + <0 0 0 0 0 0 480000000 0 0 0 600000000 0>; + clock-cntl-level = "svs", "turbo"; + src-clock-name = "ife_csid_clk_src"; + ppi-enable; + status = "ok"; + }; + + cam_vfe_lite: qcom,vfe-lite@acc4000 { + cell-index = <2>; + compatible = "qcom,vfe-lite170"; + reg-names = "ife-lite"; + reg = <0xacc4000 0x4000>; + reg-cam-base = <0xc4000>; + interrupt-names = "ife-lite"; + interrupts = <0 472 0>; + regulator-names = "camss"; + camss-supply = <&titan_top_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "slow_ahb_clk_src", + "ife_clk", + "ife_clk_src", + "camnoc_axi_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 360000000 0>, + <0 0 0 0 0 0 432000000 0>, + <0 0 0 0 0 0 600000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc@ac4e000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac4e000 0x4000>; + reg-cam-base = <0x4e000>; + interrupt-names = "jpeg"; + interrupts = <0 474 0>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "camnoc_axi_clk", + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + + clock-rates = <0 0 0 0 0 600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "turbo"; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma@ac52000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac52000 0x4000>; + reg-cam-base = <0x52000>; + interrupt-names = "jpegdma"; + interrupts = <0 475 0>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&titan_top_gdsc>; + clock-names = "camera_ahb", + "camera_axi", + "soc_ahb_clk", + "cpas_ahb_clk", + "camnoc_axi_clk", + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + + clock-rates = <0 0 0 0 0 600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "turbo"; + status = "ok"; + }; + + cam_ppi0: qcom,ppi0@ace0000 { + cell-index = <0>; + compatible = "qcom,ppi170"; + reg-names = "ppi"; + reg = <0xace0000 0x200>; + reg-cam-base = <0xe0000>; + interrupt-names = "ppi"; + interrupts = <0 170 0>; + clocks = <&clock_camcc CAM_CC_CSIPHY0_CLK>; + clock-names = "csiphy0_clk"; + status = "ok"; + }; + + cam_ppi1: qcom,ppi0@ace0200 { + cell-index = <1>; + compatible = "qcom,ppi170"; + reg-names = "ppi"; + reg = <0xace0200 0x200>; + reg-cam-base = <0xe0200>; + interrupt-names = "ppi"; + interrupts = <0 171 0>; + clocks = <&clock_camcc CAM_CC_CSIPHY1_CLK>; + clock-names = "csiphy1_clk"; + status = "ok"; + }; + + cam_ppi2: qcom,ppi0@ace0400 { + cell-index = <2>; + compatible = "qcom,ppi170"; + reg-names = "ppi"; + reg = <0xace0400 0x200>; + reg-cam-base = <0xe0400>; + interrupt-names = "ppi"; + interrupts = <0 172 0>; + clocks = <&clock_camcc CAM_CC_CSIPHY2_CLK>; + clock-names = "csiphy2_clk"; + status = "ok"; + }; + + cam_ppi3: qcom,ppi0@ace0600 { + cell-index = <3>; + compatible = "qcom,ppi170"; + reg-names = "ppi"; + reg = <0xace0600 0x200>; + reg-cam-base = <0xe00600>; + interrupt-names = "ppi"; + interrupts = <0 173 0>; + clocks = <&clock_camcc CAM_CC_CSIPHY3_CLK>; + clock-names = "csiphy3_clk"; + status = "ok"; + }; +}; From 86e93bf9252372ca4c0342dd4afcdfe6b02d0939 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Thu, 1 Aug 2019 12:57:16 +0530 Subject: [PATCH 11/15] ARM: dts: msm: Add PPI clock sources to bring up v150_110 camera PPI clock sources are added for chipsets having v150_110 camera. Change-Id: Ibab7f009fce45ea309f13501efb2f16fafb87ed6 Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/atoll-camera.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/atoll-camera.dtsi b/arch/arm64/boot/dts/qcom/atoll-camera.dtsi index 05665defb5b28..e7e836cabaeac 100644 --- a/arch/arm64/boot/dts/qcom/atoll-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-camera.dtsi @@ -825,6 +825,8 @@ interrupts = <0 170 0>; clocks = <&clock_camcc CAM_CC_CSIPHY0_CLK>; clock-names = "csiphy0_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; status = "ok"; }; @@ -838,6 +840,8 @@ interrupts = <0 171 0>; clocks = <&clock_camcc CAM_CC_CSIPHY1_CLK>; clock-names = "csiphy1_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; status = "ok"; }; @@ -851,6 +855,8 @@ interrupts = <0 172 0>; clocks = <&clock_camcc CAM_CC_CSIPHY2_CLK>; clock-names = "csiphy2_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; status = "ok"; }; @@ -864,6 +870,8 @@ interrupts = <0 173 0>; clocks = <&clock_camcc CAM_CC_CSIPHY3_CLK>; clock-names = "csiphy3_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; status = "ok"; }; }; From cc2b54e2fac930409b55c8104686ce2e652f99e2 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Mon, 5 Aug 2019 17:50:58 +0530 Subject: [PATCH 12/15] ARM: dts: msm: Add AHB-IB voting bandwidth to bring up v150_110 camera AHB-IB bandwidth are added for chipsets having v150_110 camera. Change-Id: I6df5d35fa5c9bf2f7b056f9f5333147c3564fa00 Signed-off-by: Chandan Kumar Jha --- arch/arm64/boot/dts/qcom/atoll-camera.dtsi | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/atoll-camera.dtsi b/arch/arm64/boot/dts/qcom/atoll-camera.dtsi index e7e836cabaeac..36e7efcb00821 100644 --- a/arch/arm64/boot/dts/qcom/atoll-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-camera.dtsi @@ -203,29 +203,26 @@ <0 0 0 80000000 0 0>, <0 0 0 80000000 0 0>, <0 0 0 80000000 0 0>, - <0 0 0 80000000 0 0>, <0 0 0 80000000 0 0>; - clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; //qcom,cam-cx-ipeak = <&cx_ipeak_lm 2>; qcom,msm-bus,name = "cam_ahb"; - qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-cases = <6>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = , , - , + MSM_BUS_SLAVE_CAMERA_CFG 0 89500>, , + MSM_BUS_SLAVE_CAMERA_CFG 0 125000>, , + MSM_BUS_SLAVE_CAMERA_CFG 0 125000>, , + MSM_BUS_SLAVE_CAMERA_CFG 0 250000>, ; + MSM_BUS_SLAVE_CAMERA_CFG 0 250000>; vdd-corners = ; vdd-corner-ahb-mapping = "suspend", "suspend", - "minsvs", "lowsvs", "svs", "svs_l1", + "lowsvs", "lowsvs", "svs", "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; client-id-based; From 6e0da9fb368a862e953f0ed9738110aecb82ce10 Mon Sep 17 00:00:00 2001 From: Shankar Ravi Date: Fri, 26 Jul 2019 19:48:51 +0530 Subject: [PATCH 13/15] ARM: dts: qcom: Add csiphy, cci for atoll Add CCI,CSIPHY hardware nodes, clocks, gpios to control the camera sensors for atoll. Change-Id: I6f2272070941686c06ec52d964a968123ce6ded5 Signed-off-by: Shankar Ravi --- .../bindings/media/video/msm-cam-csiphy.txt | 3 +- arch/arm64/boot/dts/qcom/atoll-camera.dtsi | 352 ++++++++++++++++++ 2 files changed, 354 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt b/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt index 0b00cc025f00c..a75935c1e3b85 100644 --- a/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt +++ b/Documentation/devicetree/bindings/media/video/msm-cam-csiphy.txt @@ -15,7 +15,8 @@ First Level Node - CSIPHY device Value type: Definition: Should be "qcom,csiphy-v1.0", "qcom,csiphy-v1.1", "qcom,csiphy-v1.2", - "qcom,csiphy-v2.0", "qcom,csiphy". + "qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", + "qcom,csiphy". - cell-index: csiphy hardware core index Usage: required diff --git a/arch/arm64/boot/dts/qcom/atoll-camera.dtsi b/arch/arm64/boot/dts/qcom/atoll-camera.dtsi index 36e7efcb00821..1cfc8a0aed71c 100644 --- a/arch/arm64/boot/dts/qcom/atoll-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-camera.dtsi @@ -17,6 +17,358 @@ status = "ok"; }; + cam_csiphy0: qcom,csiphy@ac65000 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy"; + reg = <0x0ac65000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x65000>; + interrupts = <0 477 0>; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-voltage = <900000>; + mipi-csi-vdd-supply = <&L4A>; + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-rates = + <0 0 0 0 270000000 0 300000000 0>, + <0 0 0 0 360000000 0 300000000 0>, + <0 0 0 0 360000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy@ac66000{ + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy"; + reg = <0xac66000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x66000>; + interrupts = <0 478 0>; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-voltage = <900000>; + mipi-csi-vdd-supply = <&L4A>; + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-rates = + <0 0 0 0 270000000 0 300000000 0>, + <0 0 0 0 360000000 0 300000000 0>, + <0 0 0 0 360000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy@ac67000 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy"; + reg = <0xac67000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x67000>; + interrupts = <0 479 0>; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-voltage = <900000>; + mipi-csi-vdd-supply = <&L4A>; + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-rates = + <0 0 0 0 270000000 0 300000000 0>, + <0 0 0 0 360000000 0 300000000 0>, + <0 0 0 0 360000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy@ac68000 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy"; + reg = <0xac68000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x68000>; + interrupts = <0 461 0>; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen"; + gdscr-supply = <&titan_top_gdsc>; + refgen-supply = <&refgen>; + csi-vdd-voltage = <900000>; + mipi-csi-vdd-supply = <&L4A>; + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "svs", "svs_l1", "turbo"; + clock-rates = + <0 0 0 0 270000000 0 300000000 0>, + <0 0 0 0 360000000 0 300000000 0>, + <0 0 0 0 360000000 0 300000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci@ac4a000 { + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0xac4a000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4a000>; + interrupt-names = "cci"; + interrupts = <0 468 0>; + status = "ok"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CCI_0_CLK>, + <&clock_camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cci_clk", + "cci_clk_src"; + src-clock-name = "cci_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 0 0 0 0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 17 0>, + <&tlmm 18 0>, + <&tlmm 19 0>, + <&tlmm 20 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci@ac4b000 { + cell-index = <1>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4b000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4b000>; + interrupt-names = "cci"; + interrupts = <0 462 0>; + status = "ok"; + gdscr-supply = <&titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CCI_1_CLK>, + <&clock_camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi_clk", + "soc_ahb_clk", + "slow_ahb_src_clk", + "cpas_ahb_clk", + "cci_clk", + "cci_clk_src"; + src-clock-name = "cci_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 0 0 0 0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 28 0>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + qcom,cam_smmu { compatible = "qcom,msm-cam-smmu"; status = "ok"; From 630b6773460347e8f802d649a9a7b2f703f57818 Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Mon, 5 Aug 2019 14:46:22 +0530 Subject: [PATCH 14/15] ARM: dts: qcom: Enable phy regulators for atoll Enable and add csiphy regulators in csiphy nodes for atoll. Change-Id: Ic394ee0be86fb1b0cba8a51a8b134eb426681c78 Signed-off-by: Shravan Nevatia --- arch/arm64/boot/dts/qcom/atoll-camera.dtsi | 44 ++++++++++++++++------ 1 file changed, 32 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/atoll-camera.dtsi b/arch/arm64/boot/dts/qcom/atoll-camera.dtsi index 1cfc8a0aed71c..020032d19482c 100644 --- a/arch/arm64/boot/dts/qcom/atoll-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/atoll-camera.dtsi @@ -25,11 +25,16 @@ reg-cam-base = <0x65000>; interrupts = <0 477 0>; interrupt-names = "csiphy"; - regulator-names = "gdscr", "refgen"; + regulator-names = "gdscr", "refgen", + "mipi-csi-vdd1", "mipi-csi-vdd2"; gdscr-supply = <&titan_top_gdsc>; refgen-supply = <&refgen>; - csi-vdd-voltage = <900000>; - mipi-csi-vdd-supply = <&L4A>; + mipi-csi-vdd1-supply = <&L4A>; + mipi-csi-vdd2-supply = <&L3C>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 900000 1200000>; + rgltr-max-voltage = <0 0 900000 1200000>; + rgltr-load-current = <0 0 80000 80000>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, @@ -63,11 +68,16 @@ reg-cam-base = <0x66000>; interrupts = <0 478 0>; interrupt-names = "csiphy"; - regulator-names = "gdscr", "refgen"; + regulator-names = "gdscr", "refgen", + "mipi-csi-vdd1", "mipi-csi-vdd2"; gdscr-supply = <&titan_top_gdsc>; refgen-supply = <&refgen>; - csi-vdd-voltage = <900000>; - mipi-csi-vdd-supply = <&L4A>; + mipi-csi-vdd1-supply = <&L4A>; + mipi-csi-vdd2-supply = <&L3C>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 900000 1200000>; + rgltr-max-voltage = <0 0 900000 1200000>; + rgltr-load-current = <0 0 80000 80000>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, @@ -101,11 +111,16 @@ reg-cam-base = <0x67000>; interrupts = <0 479 0>; interrupt-names = "csiphy"; - regulator-names = "gdscr", "refgen"; + regulator-names = "gdscr", "refgen", + "mipi-csi-vdd1", "mipi-csi-vdd2"; gdscr-supply = <&titan_top_gdsc>; refgen-supply = <&refgen>; - csi-vdd-voltage = <900000>; - mipi-csi-vdd-supply = <&L4A>; + mipi-csi-vdd1-supply = <&L4A>; + mipi-csi-vdd2-supply = <&L3C>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 900000 1200000>; + rgltr-max-voltage = <0 0 900000 1200000>; + rgltr-load-current = <0 0 80000 80000>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, @@ -139,11 +154,16 @@ reg-cam-base = <0x68000>; interrupts = <0 461 0>; interrupt-names = "csiphy"; - regulator-names = "gdscr", "refgen"; + regulator-names = "gdscr", "refgen", + "mipi-csi-vdd1", "mipi-csi-vdd2"; gdscr-supply = <&titan_top_gdsc>; refgen-supply = <&refgen>; - csi-vdd-voltage = <900000>; - mipi-csi-vdd-supply = <&L4A>; + mipi-csi-vdd1-supply = <&L4A>; + mipi-csi-vdd2-supply = <&L3C>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 900000 1200000>; + rgltr-max-voltage = <0 0 900000 1200000>; + rgltr-load-current = <0 0 80000 80000>; clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, <&clock_camcc CAM_CC_SOC_AHB_CLK>, <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, From 5ec379ba4f2c93e26a5687c9c4c0a24907a6b190 Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Thu, 8 Aug 2019 15:56:54 +0530 Subject: [PATCH 15/15] ARM: dts: msm: Add camera sensor nodes for atoll Add sensor, actuator, eeprom and flash nodes for atoll Change-Id: I754c9396dae6d2635bd092ca816591f956624076 Signed-off-by: Shravan Nevatia --- .../dts/qcom/atoll-camera-sensor-idp.dtsi | 256 ++++++++++++++++++ .../dts/qcom/atoll-camera-sensor-idps.dtsi | 256 ++++++++++++++++++ 2 files changed, 512 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/atoll-camera-sensor-idp.dtsi create mode 100644 arch/arm64/boot/dts/qcom/atoll-camera-sensor-idps.dtsi diff --git a/arch/arm64/boot/dts/qcom/atoll-camera-sensor-idp.dtsi b/arch/arm64/boot/dts/qcom/atoll-camera-sensor-idp.dtsi new file mode 100644 index 0000000000000..8658ece3bb2f5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/atoll-camera-sensor-idp.dtsi @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2 &pm6150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2 &pm6150l_switch2>; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L6P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&L6P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0>; + rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + actuator-src = <&actuator_rear>; + cam_vio-supply = <&L5P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0>; + rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + cam_vio-supply = <&L5P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0>; + rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x2>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L5P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0>; + rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 29 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/atoll-camera-sensor-idps.dtsi b/arch/arm64/boot/dts/qcom/atoll-camera-sensor-idps.dtsi new file mode 100644 index 0000000000000..7a90148002ce4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/atoll-camera-sensor-idps.dtsi @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + reg = <0x00 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2 &pm6150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + reg = <0x01 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2 &pm6150l_switch2>; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; + + actuator_rear: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L6P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + }; + + eeprom_rear: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&L6P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L5P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0>; + rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + actuator-src = <&actuator_rear>; + cam_vio-supply = <&L5P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0>; + rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 30 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux>; + cam_vio-supply = <&L5P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0>; + rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x2>; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L5P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0>; + rgltr-max-voltage = <1800000 2800000 1104000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +};