diff --git a/CHANGELOG.md b/CHANGELOG.md
index cd6a5b38..65498e50 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Changed
 
 - `timer.rs` refactoring
+- Demacrofy `RxDma`/`TxDma` implementations
 
 ## [v0.11.0] - 2025-09-09
 
diff --git a/src/adc.rs b/src/adc.rs
index 05ac87a6..ba025620 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -5,9 +5,6 @@ use core::ops::Deref;
 use embedded_hal_02::adc::{Channel, OneShot};
 use fugit::HertzU32 as Hertz;
 
-#[cfg(all(feature = "stm32f103", any(feature = "high", feature = "xl")))]
-use crate::dma::dma2;
-use crate::dma::{dma1, CircBuffer, Receive, RxDma, Transfer, TransferPayload, W};
 use crate::gpio::{self, Analog};
 use crate::rcc::{Enable, Rcc, Reset};
 use crate::time::kHz;
@@ -18,6 +15,9 @@ use embedded_dma::WriteBuffer;
 use crate::pac::{self, RCC};
 use crate::pacext::adc::{AdcRB, Cr1W, Cr2R, Cr2W, Dr, ExtSelW};
 
+mod dma;
+pub use dma::*;
+
 const TEMP_CHANNEL: u8 = 16;
 const VREF_CHANNEL: u8 = 17;
 
@@ -609,12 +609,6 @@ impl Adc<pac::ADC1> {
     }
 }
 
-pub struct AdcPayload<ADC, PINS, MODE> {
-    adc: Adc<ADC>,
-    pins: PINS,
-    _mode: PhantomData<MODE>,
-}
-
 pub trait ChannelTimeSequence {
     /// Set ADC sampling time for particular channel
     fn set_channel_sample_time(&mut self, chan: u8, sample_time: SampleTime);
@@ -655,221 +649,3 @@ pub trait SetChannels<PINS>: ChannelTimeSequence {
     fn set_samples(&mut self);
     fn set_sequence(&mut self);
 }
-
-pub type AdcDma<ADC, PINS, MODE, CHANNEL> = RxDma<AdcPayload<ADC, PINS, MODE>, CHANNEL>;
-
-macro_rules! adcdma {
-    ($ADCX:ty: (
-        $rxdma:ident,
-        $dmarxch:ty,
-    )) => {
-        pub type $rxdma<PINS, MODE> = AdcDma<$ADCX, PINS, MODE, $dmarxch>;
-
-        impl<PINS, MODE> Receive for AdcDma<$ADCX, PINS, MODE, $dmarxch> {
-            type RxChannel = $dmarxch;
-            type TransmittedWord = u16;
-        }
-
-        impl<PINS> TransferPayload for AdcDma<$ADCX, PINS, Continuous, $dmarxch> {
-            fn start(&mut self) {
-                self.channel.start();
-                self.payload.adc.rb.cr2().modify(|_, w| w.cont().set_bit());
-                self.payload.adc.rb.cr2().modify(|_, w| w.adon().set_bit());
-            }
-            fn stop(&mut self) {
-                self.channel.stop();
-                self.payload
-                    .adc
-                    .rb
-                    .cr2()
-                    .modify(|_, w| w.cont().clear_bit());
-            }
-        }
-
-        impl<PINS> TransferPayload for AdcDma<$ADCX, PINS, Scan, $dmarxch> {
-            fn start(&mut self) {
-                self.channel.start();
-                self.payload.adc.rb.cr2().modify(|_, w| w.adon().set_bit());
-            }
-            fn stop(&mut self) {
-                self.channel.stop();
-            }
-        }
-
-        impl Adc<$ADCX> {
-            pub fn with_dma<PIN>(
-                mut self,
-                pins: PIN,
-                dma_ch: $dmarxch,
-            ) -> AdcDma<$ADCX, PIN, Continuous, $dmarxch>
-            where
-                PIN: Channel<$ADCX, ID = u8>,
-            {
-                self.rb.cr1().modify(|_, w| w.discen().clear_bit());
-                self.rb
-                    .cr2()
-                    .modify(|_, w| w.align().variant(self.align.into()));
-                self.set_channel_sample_time(PIN::channel(), self.sample_time);
-                self.rb
-                    .sqr3()
-                    .modify(|_, w| unsafe { w.sq1().bits(PIN::channel()) });
-                self.rb.cr2().modify(|_, w| w.dma().set_bit());
-
-                let payload = AdcPayload {
-                    adc: self,
-                    pins,
-                    _mode: PhantomData,
-                };
-                RxDma {
-                    payload,
-                    channel: dma_ch,
-                }
-            }
-
-            pub fn with_scan_dma<PINS>(
-                mut self,
-                pins: PINS,
-                dma_ch: $dmarxch,
-            ) -> AdcDma<$ADCX, PINS, Scan, $dmarxch>
-            where
-                Self: SetChannels<PINS>,
-            {
-                self.rb.cr2().modify(|_, w| {
-                    w.adon().clear_bit();
-                    w.dma().clear_bit();
-                    w.cont().clear_bit();
-                    w.align().variant(self.align.into())
-                });
-                self.rb
-                    .cr1()
-                    .modify(|_, w| w.scan().set_bit().discen().clear_bit());
-                self.set_samples();
-                self.set_sequence();
-                self.rb
-                    .cr2()
-                    .modify(|_, w| w.dma().set_bit().adon().set_bit());
-
-                let payload = AdcPayload {
-                    adc: self,
-                    pins,
-                    _mode: PhantomData,
-                };
-                RxDma {
-                    payload,
-                    channel: dma_ch,
-                }
-            }
-        }
-
-        impl<PINS> AdcDma<$ADCX, PINS, Continuous, $dmarxch>
-        where
-            Self: TransferPayload,
-        {
-            pub fn split(mut self) -> (Adc<$ADCX>, PINS, $dmarxch) {
-                self.stop();
-
-                let AdcDma { payload, channel } = self;
-                payload.adc.rb.cr2().modify(|_, w| w.dma().clear_bit());
-                payload.adc.rb.cr1().modify(|_, w| w.discen().set_bit());
-
-                (payload.adc, payload.pins, channel)
-            }
-        }
-
-        impl<PINS> AdcDma<$ADCX, PINS, Scan, $dmarxch>
-        where
-            Self: TransferPayload,
-        {
-            pub fn split(mut self) -> (Adc<$ADCX>, PINS, $dmarxch) {
-                self.stop();
-
-                let AdcDma { payload, channel } = self;
-                payload.adc.rb.cr2().modify(|_, w| w.dma().clear_bit());
-                payload.adc.rb.cr1().modify(|_, w| w.discen().set_bit());
-                payload.adc.rb.cr1().modify(|_, w| w.scan().clear_bit());
-
-                (payload.adc, payload.pins, channel)
-            }
-        }
-
-        impl<B, PINS, MODE> crate::dma::CircReadDma<B, u16> for AdcDma<$ADCX, PINS, MODE, $dmarxch>
-        where
-            Self: TransferPayload,
-            &'static mut [B; 2]: WriteBuffer<Word = u16>,
-            B: 'static,
-        {
-            fn circ_read(mut self, mut buffer: &'static mut [B; 2]) -> CircBuffer<B, Self> {
-                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
-                // until the end of the transfer.
-                let (ptr, len) = unsafe { buffer.write_buffer() };
-                self.channel.set_peripheral_address(
-                    unsafe { (*<$ADCX>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-                self.channel.set_memory_address(ptr as u32, true);
-                self.channel.set_transfer_length(len);
-
-                atomic::compiler_fence(Ordering::Release);
-
-                self.channel.ch().cr().modify(|_, w| {
-                    w.mem2mem().clear_bit();
-                    w.pl().medium();
-                    w.msize().bits16();
-                    w.psize().bits16();
-                    w.circ().set_bit();
-                    w.dir().clear_bit()
-                });
-
-                self.start();
-
-                CircBuffer::new(buffer, self)
-            }
-        }
-
-        impl<B, PINS, MODE> crate::dma::ReadDma<B, u16> for AdcDma<$ADCX, PINS, MODE, $dmarxch>
-        where
-            Self: TransferPayload,
-            B: WriteBuffer<Word = u16>,
-        {
-            fn read(mut self, mut buffer: B) -> Transfer<W, B, Self> {
-                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
-                // until the end of the transfer.
-                let (ptr, len) = unsafe { buffer.write_buffer() };
-                self.channel.set_peripheral_address(
-                    unsafe { (*<$ADCX>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-                self.channel.set_memory_address(ptr as u32, true);
-                self.channel.set_transfer_length(len);
-
-                atomic::compiler_fence(Ordering::Release);
-                self.channel.ch().cr().modify(|_, w| {
-                    w.mem2mem().clear_bit();
-                    w.pl().medium();
-                    w.msize().bits16();
-                    w.psize().bits16();
-                    w.circ().clear_bit();
-                    w.dir().clear_bit()
-                });
-                self.start();
-
-                Transfer::w(buffer, self)
-            }
-        }
-    };
-}
-
-adcdma! {
-    pac::ADC1: (
-        AdcDma1,
-        dma1::C1,
-    )
-}
-
-#[cfg(all(feature = "stm32f103", any(feature = "high", feature = "xl")))]
-adcdma! {
-    pac::ADC3: (
-        AdcDma3,
-        dma2::C5,
-    )
-}
diff --git a/src/adc/dma.rs b/src/adc/dma.rs
new file mode 100644
index 00000000..6a9651c4
--- /dev/null
+++ b/src/adc/dma.rs
@@ -0,0 +1,227 @@
+use super::*;
+
+#[cfg(all(feature = "stm32f103", any(feature = "high", feature = "xl")))]
+use crate::dma::dma2;
+use crate::dma::{dma1, Ch, CircBuffer, DmaExt, Receive, RxDma, Transfer, TransferPayload, W};
+
+pub struct AdcPayload<ADC, PINS, MODE> {
+    adc: Adc<ADC>,
+    pins: PINS,
+    _mode: PhantomData<MODE>,
+}
+
+pub type AdcDma<ADC, PINS, MODE, CHANNEL> = RxDma<AdcPayload<ADC, PINS, MODE>, CHANNEL>;
+
+impl<ADC: Instance, PINS, DMA: DmaExt, const C: u8> TransferPayload
+    for AdcDma<ADC, PINS, Continuous, Ch<DMA, C>>
+{
+    fn start(&mut self) {
+        self.channel.start();
+        self.payload.adc.rb.cr2().modify(|_, w| w.cont().set_bit());
+        self.payload.adc.rb.cr2().modify(|_, w| w.adon().set_bit());
+    }
+    fn stop(&mut self) {
+        self.channel.stop();
+        self.payload
+            .adc
+            .rb
+            .cr2()
+            .modify(|_, w| w.cont().clear_bit());
+    }
+}
+
+impl<ADC: Instance, PINS, DMA: DmaExt, const C: u8> TransferPayload
+    for AdcDma<ADC, PINS, Scan, Ch<DMA, C>>
+{
+    fn start(&mut self) {
+        self.channel.start();
+        self.payload.adc.rb.cr2().modify(|_, w| w.adon().set_bit());
+    }
+    fn stop(&mut self) {
+        self.channel.stop();
+    }
+}
+
+impl<ADC: Instance> Adc<ADC> {
+    pub fn with_dma<PIN, CH>(mut self, pins: PIN, dma_ch: CH) -> AdcDma<ADC, PIN, Continuous, CH>
+    where
+        AdcPayload<ADC, PIN, Continuous>: Receive<RxChannel = CH>,
+        PIN: Channel<ADC, ID = u8>,
+    {
+        self.rb.cr1().modify(|_, w| w.discen().clear_bit());
+        self.rb
+            .cr2()
+            .modify(|_, w| w.align().variant(self.align.into()));
+        self.set_channel_sample_time(PIN::channel(), self.sample_time);
+        self.rb
+            .sqr3()
+            .modify(|_, w| unsafe { w.sq1().bits(PIN::channel()) });
+        self.rb.cr2().modify(|_, w| w.dma().set_bit());
+
+        let payload = AdcPayload {
+            adc: self,
+            pins,
+            _mode: PhantomData,
+        };
+        RxDma {
+            payload,
+            channel: dma_ch,
+        }
+    }
+
+    pub fn with_scan_dma<PINS, CH>(mut self, pins: PINS, dma_ch: CH) -> AdcDma<ADC, PINS, Scan, CH>
+    where
+        AdcPayload<ADC, PINS, Scan>: Receive<RxChannel = CH>,
+        Self: SetChannels<PINS>,
+    {
+        self.rb.cr2().modify(|_, w| {
+            w.adon().clear_bit();
+            w.dma().clear_bit();
+            w.cont().clear_bit();
+            w.align().variant(self.align.into())
+        });
+        self.rb
+            .cr1()
+            .modify(|_, w| w.scan().set_bit().discen().clear_bit());
+        self.set_samples();
+        self.set_sequence();
+        self.rb
+            .cr2()
+            .modify(|_, w| w.dma().set_bit().adon().set_bit());
+
+        let payload = AdcPayload {
+            adc: self,
+            pins,
+            _mode: PhantomData,
+        };
+        RxDma {
+            payload,
+            channel: dma_ch,
+        }
+    }
+}
+
+impl<ADC: Instance, PINS, CH> AdcDma<ADC, PINS, Continuous, CH>
+where
+    Self: TransferPayload,
+{
+    pub fn split(mut self) -> (Adc<ADC>, PINS, CH) {
+        self.stop();
+
+        let AdcDma { payload, channel } = self;
+        payload.adc.rb.cr2().modify(|_, w| w.dma().clear_bit());
+        payload.adc.rb.cr1().modify(|_, w| w.discen().set_bit());
+
+        (payload.adc, payload.pins, channel)
+    }
+}
+
+impl<ADC: Instance, PINS, CH> AdcDma<ADC, PINS, Scan, CH>
+where
+    Self: TransferPayload,
+{
+    pub fn split(mut self) -> (Adc<ADC>, PINS, CH) {
+        self.stop();
+
+        let AdcDma { payload, channel } = self;
+        payload.adc.rb.cr2().modify(|_, w| w.dma().clear_bit());
+        payload.adc.rb.cr1().modify(|_, w| w.discen().set_bit());
+        payload.adc.rb.cr1().modify(|_, w| w.scan().clear_bit());
+
+        (payload.adc, payload.pins, channel)
+    }
+}
+
+impl<ADC: Instance, B, PINS, MODE, DMA: DmaExt, const C: u8> crate::dma::CircReadDma<B, u16>
+    for AdcDma<ADC, PINS, MODE, Ch<DMA, C>>
+where
+    AdcPayload<ADC, PINS, MODE>: Receive<RxChannel = Ch<DMA, C>>,
+    Self: TransferPayload,
+    &'static mut [B; 2]: WriteBuffer<Word = u16>,
+    B: 'static,
+{
+    fn circ_read(mut self, mut buffer: &'static mut [B; 2]) -> CircBuffer<B, Self> {
+        // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
+        // until the end of the transfer.
+        let (ptr, len) = unsafe { buffer.write_buffer() };
+        self.channel
+            .set_peripheral_address(unsafe { (*ADC::ptr()).dr().as_ptr() as u32 }, false);
+        self.channel.set_memory_address(ptr as u32, true);
+        self.channel.set_transfer_length(len);
+
+        atomic::compiler_fence(Ordering::Release);
+
+        self.channel.ch().cr().modify(|_, w| {
+            w.mem2mem().clear_bit();
+            w.pl().medium();
+            w.msize().bits16();
+            w.psize().bits16();
+            w.circ().set_bit();
+            w.dir().clear_bit()
+        });
+
+        self.start();
+
+        CircBuffer::new(buffer, self)
+    }
+}
+
+impl<ADC: Instance, B, PINS, MODE, DMA: DmaExt, const C: u8> crate::dma::ReadDma<B, u16>
+    for AdcDma<ADC, PINS, MODE, Ch<DMA, C>>
+where
+    AdcPayload<ADC, PINS, MODE>: Receive<RxChannel = Ch<DMA, C>>,
+    Self: TransferPayload,
+    B: WriteBuffer<Word = u16>,
+{
+    fn read(mut self, mut buffer: B) -> Transfer<W, B, Self> {
+        // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
+        // until the end of the transfer.
+        let (ptr, len) = unsafe { buffer.write_buffer() };
+        self.channel
+            .set_peripheral_address(unsafe { (*ADC::ptr()).dr().as_ptr() as u32 }, false);
+        self.channel.set_memory_address(ptr as u32, true);
+        self.channel.set_transfer_length(len);
+
+        atomic::compiler_fence(Ordering::Release);
+        self.channel.ch().cr().modify(|_, w| {
+            w.mem2mem().clear_bit();
+            w.pl().medium();
+            w.msize().bits16();
+            w.psize().bits16();
+            w.circ().clear_bit();
+            w.dir().clear_bit()
+        });
+        self.start();
+
+        Transfer::w(buffer, self)
+    }
+}
+
+macro_rules! adcdma {
+    ($ADCX:ty: (
+        $rxdma:ident,
+        $dmarxch:ty,
+    )) => {
+        pub type $rxdma<PINS, MODE> = AdcDma<$ADCX, PINS, MODE, $dmarxch>;
+
+        impl<PINS, MODE> Receive for AdcPayload<$ADCX, PINS, MODE> {
+            type RxChannel = $dmarxch;
+            type TransmittedWord = u16;
+        }
+    };
+}
+
+adcdma! {
+    pac::ADC1: (
+        AdcDma1,
+        dma1::C1,
+    )
+}
+
+#[cfg(all(feature = "stm32f103", any(feature = "high", feature = "xl")))]
+adcdma! {
+    pac::ADC3: (
+        AdcDma3,
+        dma2::C5,
+    )
+}
diff --git a/src/dma.rs b/src/dma.rs
index c90ac132..e7a196f9 100644
--- a/src/dma.rs
+++ b/src/dma.rs
@@ -553,3 +553,35 @@ where
 {
     fn read_write(self, rx_buffer: RXB, tx_buffer: TXB) -> Transfer<W, (RXB, TXB), Self>;
 }
+
+impl<P, CH, W> Receive for RxDma<P, CH>
+where
+    P: Receive<RxChannel = CH, TransmittedWord = W>,
+{
+    type RxChannel = CH;
+    type TransmittedWord = W;
+}
+
+impl<P, CH, W> Transmit for TxDma<P, CH>
+where
+    P: Transmit<TxChannel = CH, ReceivedWord = W>,
+{
+    type TxChannel = CH;
+    type ReceivedWord = W;
+}
+
+impl<P, RXCH, TXCH, W> Receive for RxTxDma<P, RXCH, TXCH>
+where
+    P: Receive<RxChannel = RXCH, TransmittedWord = W>,
+{
+    type RxChannel = RXCH;
+    type TransmittedWord = W;
+}
+
+impl<P, RXCH, TXCH, W> Transmit for RxTxDma<P, RXCH, TXCH>
+where
+    P: Transmit<TxChannel = TXCH, ReceivedWord = W>,
+{
+    type TxChannel = TXCH;
+    type ReceivedWord = W;
+}
diff --git a/src/lib.rs b/src/lib.rs
index d1549ca3..69580101 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -166,15 +166,18 @@ impl<RB, const A: usize> Sealed for Periph<RB, A> {}
 pub trait Ptr: Sealed {
     /// RegisterBlock structure
     type RB;
+    /// Pointer to the register block
+    const PTR: *const Self::RB;
     /// Return the pointer to the register block
-    fn ptr() -> *const Self::RB;
+    #[inline(always)]
+    fn ptr() -> *const Self::RB {
+        Self::PTR
+    }
 }
 
 impl<RB, const A: usize> Ptr for Periph<RB, A> {
     type RB = RB;
-    fn ptr() -> *const Self::RB {
-        Self::ptr()
-    }
+    const PTR: *const Self::RB = Self::PTR;
 }
 
 pub trait Steal: Sealed {
@@ -195,6 +198,7 @@ pub trait Steal: Sealed {
 }
 
 impl<RB, const A: usize> Steal for Periph<RB, A> {
+    #[inline(always)]
     unsafe fn steal() -> Self {
         Self::steal()
     }
diff --git a/src/serial.rs b/src/serial.rs
index 838036dd..6763ca63 100644
--- a/src/serial.rs
+++ b/src/serial.rs
@@ -95,16 +95,15 @@ use core::sync::atomic::{self, Ordering};
 use embedded_dma::{ReadBuffer, WriteBuffer};
 
 use crate::afio::{self, RInto, Rmp};
-#[cfg(any(all(feature = "stm32f103", feature = "high"), feature = "connectivity"))]
-use crate::dma::dma2;
-use crate::dma::{self, dma1, CircBuffer, RxDma, Transfer, TxDma};
 use crate::gpio::{Floating, PushPull, UpMode};
 use crate::pac::{self};
 use crate::rcc::{BusClock, Clocks, Enable, Rcc, Reset};
 use crate::time::{Bps, U32Ext};
 
+mod dma;
 mod hal_02;
 mod hal_1;
+pub use dma::*;
 
 use crate::pacext::uart::{SrR, UartRB};
 
@@ -830,222 +829,3 @@ pub type Rx2 = Rx<pac::USART2>;
 pub type Tx2 = Tx<pac::USART2>;
 pub type Rx3 = Rx<pac::USART3>;
 pub type Tx3 = Tx<pac::USART3>;
-
-use crate::dma::{Receive, TransferPayload, Transmit};
-
-macro_rules! serialdma {
-    (
-        $USARTX:ty,
-        $rxdma:ident,
-        $txdma:ident,
-        rx: $dmarxch:ty,
-        tx: $dmatxch:ty
-    ) => {
-        pub type $rxdma = RxDma<Rx<$USARTX>, $dmarxch>;
-        pub type $txdma = TxDma<Tx<$USARTX>, $dmatxch>;
-
-        impl Receive for $rxdma {
-            type RxChannel = $dmarxch;
-            type TransmittedWord = u8;
-        }
-
-        impl Transmit for $txdma {
-            type TxChannel = $dmatxch;
-            type ReceivedWord = u8;
-        }
-
-        impl TransferPayload for $rxdma {
-            fn start(&mut self) {
-                self.channel.start();
-            }
-            fn stop(&mut self) {
-                self.channel.stop();
-            }
-        }
-
-        impl TransferPayload for $txdma {
-            fn start(&mut self) {
-                self.channel.start();
-            }
-            fn stop(&mut self) {
-                self.channel.stop();
-            }
-        }
-
-        impl Rx<$USARTX> {
-            pub fn with_dma(self, channel: $dmarxch) -> $rxdma {
-                unsafe {
-                    (*<$USARTX>::ptr()).cr3().modify(|_, w| w.dmar().set_bit());
-                }
-                RxDma {
-                    payload: self,
-                    channel,
-                }
-            }
-        }
-
-        impl Tx<$USARTX> {
-            pub fn with_dma(self, channel: $dmatxch) -> $txdma {
-                unsafe {
-                    (*<$USARTX>::ptr()).cr3().modify(|_, w| w.dmat().set_bit());
-                }
-                TxDma {
-                    payload: self,
-                    channel,
-                }
-            }
-        }
-
-        impl $rxdma {
-            pub fn release(mut self) -> (Rx<$USARTX>, $dmarxch) {
-                self.stop();
-                unsafe {
-                    (*<$USARTX>::ptr())
-                        .cr3()
-                        .modify(|_, w| w.dmar().clear_bit());
-                }
-                let RxDma { payload, channel } = self;
-                (payload, channel)
-            }
-        }
-
-        impl $txdma {
-            pub fn release(mut self) -> (Tx<$USARTX>, $dmatxch) {
-                self.stop();
-                unsafe {
-                    (*<$USARTX>::ptr())
-                        .cr3()
-                        .modify(|_, w| w.dmat().clear_bit());
-                }
-                let TxDma { payload, channel } = self;
-                (payload, channel)
-            }
-        }
-
-        impl<B> crate::dma::CircReadDma<B, u8> for $rxdma
-        where
-            &'static mut [B; 2]: WriteBuffer<Word = u8>,
-            B: 'static,
-        {
-            fn circ_read(mut self, mut buffer: &'static mut [B; 2]) -> CircBuffer<B, Self> {
-                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
-                // until the end of the transfer.
-                let (ptr, len) = unsafe { buffer.write_buffer() };
-                self.channel.set_peripheral_address(
-                    unsafe { (*<$USARTX>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-                self.channel.set_memory_address(ptr as u32, true);
-                self.channel.set_transfer_length(len);
-
-                atomic::compiler_fence(Ordering::Release);
-
-                self.channel.ch().cr().modify(|_, w| {
-                    w.mem2mem().clear_bit();
-                    w.pl().medium();
-                    w.msize().bits8();
-                    w.psize().bits8();
-                    w.circ().set_bit();
-                    w.dir().clear_bit()
-                });
-
-                self.start();
-
-                CircBuffer::new(buffer, self)
-            }
-        }
-
-        impl<B> crate::dma::ReadDma<B, u8> for $rxdma
-        where
-            B: WriteBuffer<Word = u8>,
-        {
-            fn read(mut self, mut buffer: B) -> Transfer<dma::W, B, Self> {
-                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
-                // until the end of the transfer.
-                let (ptr, len) = unsafe { buffer.write_buffer() };
-                self.channel.set_peripheral_address(
-                    unsafe { (*<$USARTX>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-                self.channel.set_memory_address(ptr as u32, true);
-                self.channel.set_transfer_length(len);
-
-                atomic::compiler_fence(Ordering::Release);
-                self.channel.ch().cr().modify(|_, w| {
-                    w.mem2mem().clear_bit();
-                    w.pl().medium();
-                    w.msize().bits8();
-                    w.psize().bits8();
-                    w.circ().clear_bit();
-                    w.dir().clear_bit()
-                });
-                self.start();
-
-                Transfer::w(buffer, self)
-            }
-        }
-
-        impl<B> crate::dma::WriteDma<B, u8> for $txdma
-        where
-            B: ReadBuffer<Word = u8>,
-        {
-            fn write(mut self, buffer: B) -> Transfer<dma::R, B, Self> {
-                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
-                // until the end of the transfer.
-                let (ptr, len) = unsafe { buffer.read_buffer() };
-
-                self.channel.set_peripheral_address(
-                    unsafe { (*<$USARTX>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-
-                self.channel.set_memory_address(ptr as u32, true);
-                self.channel.set_transfer_length(len);
-
-                atomic::compiler_fence(Ordering::Release);
-
-                self.channel.ch().cr().modify(|_, w| {
-                    w.mem2mem().clear_bit();
-                    w.pl().medium();
-                    w.msize().bits8();
-                    w.psize().bits8();
-                    w.circ().clear_bit();
-                    w.dir().set_bit()
-                });
-                self.start();
-
-                Transfer::r(buffer, self)
-            }
-        }
-    };
-}
-
-serialdma! {
-    pac::USART1,
-    RxDma1,
-    TxDma1,
-    rx: dma1::C5,
-    tx: dma1::C4
-}
-serialdma! {
-    pac::USART2,
-    RxDma2,
-    TxDma2,
-    rx: dma1::C6,
-    tx: dma1::C7
-}
-serialdma! {
-    pac::USART3,
-    RxDma3,
-    TxDma3,
-    rx: dma1::C3,
-    tx: dma1::C2
-}
-#[cfg(any(all(feature = "stm32f103", feature = "high"), feature = "connectivity"))]
-serialdma! {
-    pac::UART4,
-    RxDma4,
-    TxDma4,
-    rx: dma2::C3,
-    tx: dma2::C5
-}
diff --git a/src/serial/dma.rs b/src/serial/dma.rs
new file mode 100644
index 00000000..9d80ab9b
--- /dev/null
+++ b/src/serial/dma.rs
@@ -0,0 +1,227 @@
+use super::*;
+#[cfg(any(all(feature = "stm32f103", feature = "high"), feature = "connectivity"))]
+use crate::dma::dma2;
+use crate::dma::{self, dma1, Ch, CircBuffer, DmaExt, RxDma, Transfer, TxDma};
+
+use crate::dma::{Receive, TransferPayload, Transmit};
+
+use crate::pacext::uart::Cr3W;
+
+impl<USART: Instance, DMA: DmaExt, const C: u8> TransferPayload for RxDma<Rx<USART>, Ch<DMA, C>> {
+    fn start(&mut self) {
+        self.channel.start();
+    }
+    fn stop(&mut self) {
+        self.channel.stop();
+    }
+}
+
+impl<USART: Instance, DMA: DmaExt, const C: u8> TransferPayload for TxDma<Tx<USART>, Ch<DMA, C>> {
+    fn start(&mut self) {
+        self.channel.start();
+    }
+    fn stop(&mut self) {
+        self.channel.stop();
+    }
+}
+
+impl<USART: Instance, CH> Rx<USART>
+where
+    Self: Receive<RxChannel = CH>,
+{
+    pub fn with_dma(self, channel: CH) -> RxDma<Self, CH> {
+        let usart = unsafe { &*USART::PTR };
+        usart.cr3().modify(|_, w| w.dmar().set_bit());
+        RxDma {
+            payload: self,
+            channel,
+        }
+    }
+}
+
+impl<USART: Instance, CH> Tx<USART>
+where
+    Self: Transmit<TxChannel = CH>,
+{
+    pub fn with_dma(self, channel: CH) -> TxDma<Self, CH> {
+        let usart = unsafe { &*USART::PTR };
+        usart.cr3().modify(|_, w| w.dmat().set_bit());
+        TxDma {
+            payload: self,
+            channel,
+        }
+    }
+}
+
+impl<USART: Instance, CH> RxDma<Rx<USART>, CH>
+where
+    Self: TransferPayload,
+{
+    pub fn release(mut self) -> (Rx<USART>, CH) {
+        self.stop();
+        let usart = unsafe { &*USART::PTR };
+        usart.cr3().modify(|_, w| w.dmar().clear_bit());
+        (self.payload, self.channel)
+    }
+}
+
+impl<USART: Instance, CH> TxDma<Tx<USART>, CH>
+where
+    Self: TransferPayload,
+{
+    pub fn release(mut self) -> (Tx<USART>, CH) {
+        self.stop();
+        let usart = unsafe { &*USART::PTR };
+        usart.cr3().modify(|_, w| w.dmat().clear_bit());
+        (self.payload, self.channel)
+    }
+}
+
+impl<USART: Instance, DMA: DmaExt, const C: u8, B> crate::dma::CircReadDma<B, u8>
+    for RxDma<Rx<USART>, Ch<DMA, C>>
+where
+    Rx<USART>: Receive<RxChannel = Ch<DMA, C>>,
+    &'static mut [B; 2]: WriteBuffer<Word = u8>,
+    B: 'static,
+{
+    fn circ_read(mut self, mut buffer: &'static mut [B; 2]) -> CircBuffer<B, Self> {
+        // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
+        // until the end of the transfer.
+        let (ptr, len) = unsafe { buffer.write_buffer() };
+        self.channel
+            .set_peripheral_address(unsafe { &*USART::PTR }.dr().as_ptr() as u32, false);
+        self.channel.set_memory_address(ptr as u32, true);
+        self.channel.set_transfer_length(len);
+
+        atomic::compiler_fence(Ordering::Release);
+
+        self.channel.ch().cr().modify(|_, w| {
+            w.mem2mem().clear_bit();
+            w.pl().medium();
+            w.msize().bits8();
+            w.psize().bits8();
+            w.circ().set_bit();
+            w.dir().clear_bit()
+        });
+
+        self.start();
+
+        CircBuffer::new(buffer, self)
+    }
+}
+
+impl<USART: Instance, DMA: DmaExt, const C: u8, B> crate::dma::ReadDma<B, u8>
+    for RxDma<Rx<USART>, Ch<DMA, C>>
+where
+    Rx<USART>: Receive<RxChannel = Ch<DMA, C>>,
+    B: WriteBuffer<Word = u8>,
+{
+    fn read(mut self, mut buffer: B) -> Transfer<dma::W, B, Self> {
+        // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
+        // until the end of the transfer.
+        let (ptr, len) = unsafe { buffer.write_buffer() };
+        self.channel
+            .set_peripheral_address(unsafe { &*USART::PTR }.dr().as_ptr() as u32, false);
+        self.channel.set_memory_address(ptr as u32, true);
+        self.channel.set_transfer_length(len);
+
+        atomic::compiler_fence(Ordering::Release);
+        self.channel.ch().cr().modify(|_, w| {
+            w.mem2mem().clear_bit();
+            w.pl().medium();
+            w.msize().bits8();
+            w.psize().bits8();
+            w.circ().clear_bit();
+            w.dir().clear_bit()
+        });
+        self.start();
+
+        Transfer::w(buffer, self)
+    }
+}
+
+impl<USART: Instance, DMA: DmaExt, const C: u8, B> crate::dma::WriteDma<B, u8>
+    for TxDma<Tx<USART>, Ch<DMA, C>>
+where
+    Tx<USART>: Transmit<TxChannel = Ch<DMA, C>>,
+    B: ReadBuffer<Word = u8>,
+{
+    fn write(mut self, buffer: B) -> Transfer<dma::R, B, Self> {
+        // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
+        // until the end of the transfer.
+        let (ptr, len) = unsafe { buffer.read_buffer() };
+
+        self.channel
+            .set_peripheral_address(unsafe { &*USART::PTR }.dr().as_ptr() as u32, false);
+
+        self.channel.set_memory_address(ptr as u32, true);
+        self.channel.set_transfer_length(len);
+
+        atomic::compiler_fence(Ordering::Release);
+
+        self.channel.ch().cr().modify(|_, w| {
+            w.mem2mem().clear_bit();
+            w.pl().medium();
+            w.msize().bits8();
+            w.psize().bits8();
+            w.circ().clear_bit();
+            w.dir().set_bit()
+        });
+        self.start();
+
+        Transfer::r(buffer, self)
+    }
+}
+
+macro_rules! serialdma {
+    (
+        $USARTX:ty,
+        $rxdma:ident,
+        $txdma:ident,
+        rx: $dmarxch:ty,
+        tx: $dmatxch:ty
+    ) => {
+        pub type $rxdma = RxDma<Rx<$USARTX>, $dmarxch>;
+        pub type $txdma = TxDma<Tx<$USARTX>, $dmatxch>;
+
+        impl Receive for Rx<$USARTX> {
+            type RxChannel = $dmarxch;
+            type TransmittedWord = u8;
+        }
+
+        impl Transmit for Tx<$USARTX> {
+            type TxChannel = $dmatxch;
+            type ReceivedWord = u8;
+        }
+    };
+}
+
+serialdma! {
+    pac::USART1,
+    RxDma1,
+    TxDma1,
+    rx: dma1::C5,
+    tx: dma1::C4
+}
+serialdma! {
+    pac::USART2,
+    RxDma2,
+    TxDma2,
+    rx: dma1::C6,
+    tx: dma1::C7
+}
+serialdma! {
+    pac::USART3,
+    RxDma3,
+    TxDma3,
+    rx: dma1::C3,
+    tx: dma1::C2
+}
+#[cfg(any(all(feature = "stm32f103", feature = "high"), feature = "connectivity"))]
+serialdma! {
+    pac::UART4,
+    RxDma4,
+    TxDma4,
+    rx: dma2::C3,
+    tx: dma2::C5
+}
diff --git a/src/spi.rs b/src/spi.rs
index b21cf823..fedc5dd3 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -62,18 +62,16 @@
   ```
 */
 
+mod dma;
 mod hal_02;
 mod hal_1;
+pub use dma::*;
 
 use core::ops::{Deref, DerefMut};
 
 use crate::pac::{self, RCC};
 
 use crate::afio::{self, RInto, Rmp};
-use crate::dma::dma1;
-#[cfg(feature = "connectivity")]
-use crate::dma::dma2;
-use crate::dma::{self, Receive, RxDma, RxTxDma, Transfer, TransferPayload, Transmit, TxDma};
 use crate::gpio::{Floating, PushPull, UpMode};
 use crate::rcc::{BusClock, Enable, Rcc, Reset};
 use crate::time::Hertz;
@@ -315,7 +313,8 @@ pub enum SpiBitFormat {
 
 pub trait Instance:
     crate::Sealed
-    + Deref<Target = crate::pac::spi1::RegisterBlock>
+    + crate::Ptr<RB = crate::pac::spi1::RegisterBlock>
+    + Deref<Target = Self::RB>
     + Enable
     + Reset
     + BusClock
@@ -796,581 +795,3 @@ where
         Ok(())
     }
 }
-
-// DMA
-
-pub type SpiTxDma<SPI, CHANNEL, PULL = Floating> = TxDma<Spi<SPI, u8, PULL>, CHANNEL>;
-pub type SpiRxDma<SPI, CHANNEL, PULL = Floating> = RxDma<Spi<SPI, u8, PULL>, CHANNEL>;
-pub type SpiRxTxDma<SPI, RXCHANNEL, TXCHANNEL, PULL = Floating> =
-    RxTxDma<Spi<SPI, u8, PULL>, RXCHANNEL, TXCHANNEL>;
-
-pub type SpiSlaveTxDma<SPI, CHANNEL, Otype, PULL = Floating> =
-    TxDma<SpiSlave<SPI, u8, Otype, PULL>, CHANNEL>;
-pub type SpiSlaveRxDma<SPI, CHANNEL, Otype, PULL = Floating> =
-    RxDma<SpiSlave<SPI, u8, Otype, PULL>, CHANNEL>;
-pub type SpiSlaveRxTxDma<SPI, RXCHANNEL, TXCHANNEL, Otype, PULL = Floating> =
-    RxTxDma<SpiSlave<SPI, u8, Otype, PULL>, RXCHANNEL, TXCHANNEL>;
-
-macro_rules! spi_dma {
-    (
-        $SPIi:ty,
-        rx: $RCi:ty,
-        tx: $TCi:ty,
-        $rxdma:ident,
-        $txdma:ident,
-        $rxtxdma:ident,
-        $slaverxdma:ident,
-        $slavetxdma:ident,
-        $slaverxtxdma:ident
-    ) => {
-        pub type $rxdma<PULL = Floating> = SpiRxDma<$SPIi, $RCi, PULL>;
-        pub type $txdma<PULL = Floating> = SpiTxDma<$SPIi, $TCi, PULL>;
-        pub type $rxtxdma<PULL = Floating> = SpiRxTxDma<$SPIi, $RCi, $TCi, PULL>;
-
-        impl<PULL> Transmit for SpiTxDma<$SPIi, $TCi, PULL> {
-            type TxChannel = $TCi;
-            type ReceivedWord = u8;
-        }
-
-        impl<PULL> Receive for SpiRxDma<$SPIi, $RCi, PULL> {
-            type RxChannel = $RCi;
-            type TransmittedWord = u8;
-        }
-
-        impl<PULL> Transmit for SpiRxTxDma<$SPIi, $RCi, $TCi, PULL> {
-            type TxChannel = $TCi;
-            type ReceivedWord = u8;
-        }
-
-        impl<PULL> Receive for SpiRxTxDma<$SPIi, $RCi, $TCi, PULL> {
-            type RxChannel = $RCi;
-            type TransmittedWord = u8;
-        }
-
-        impl<PULL> Spi<$SPIi, u8, PULL> {
-            pub fn with_tx_dma(self, channel: $TCi) -> SpiTxDma<$SPIi, $TCi, PULL> {
-                self.spi.cr2().modify(|_, w| w.txdmaen().set_bit());
-                SpiTxDma {
-                    payload: self,
-                    channel,
-                }
-            }
-            pub fn with_rx_dma(self, channel: $RCi) -> SpiRxDma<$SPIi, $RCi, PULL> {
-                self.spi.cr2().modify(|_, w| w.rxdmaen().set_bit());
-                SpiRxDma {
-                    payload: self,
-                    channel,
-                }
-            }
-            pub fn with_rx_tx_dma(
-                self,
-                rxchannel: $RCi,
-                txchannel: $TCi,
-            ) -> SpiRxTxDma<$SPIi, $RCi, $TCi, PULL> {
-                self.spi
-                    .cr2()
-                    .modify(|_, w| w.rxdmaen().set_bit().txdmaen().set_bit());
-                SpiRxTxDma {
-                    payload: self,
-                    rxchannel,
-                    txchannel,
-                }
-            }
-        }
-
-        impl<PULL> SpiTxDma<$SPIi, $TCi, PULL> {
-            pub fn release(self) -> (Spi<$SPIi, u8, PULL>, $TCi) {
-                let SpiTxDma { payload, channel } = self;
-                payload.spi.cr2().modify(|_, w| w.txdmaen().clear_bit());
-                (payload, channel)
-            }
-        }
-
-        impl<PULL> SpiRxDma<$SPIi, $RCi, PULL> {
-            pub fn release(self) -> (Spi<$SPIi, u8, PULL>, $RCi) {
-                let SpiRxDma { payload, channel } = self;
-                payload.spi.cr2().modify(|_, w| w.rxdmaen().clear_bit());
-                (payload, channel)
-            }
-        }
-
-        impl<PULL> SpiRxTxDma<$SPIi, $RCi, $TCi, PULL> {
-            pub fn release(self) -> (Spi<$SPIi, u8, PULL>, $RCi, $TCi) {
-                let SpiRxTxDma {
-                    payload,
-                    rxchannel,
-                    txchannel,
-                } = self;
-                payload
-                    .spi
-                    .cr2()
-                    .modify(|_, w| w.rxdmaen().clear_bit().txdmaen().clear_bit());
-                (payload, rxchannel, txchannel)
-            }
-        }
-
-        impl<PULL> TransferPayload for SpiTxDma<$SPIi, $TCi, PULL> {
-            fn start(&mut self) {
-                self.channel.start();
-            }
-            fn stop(&mut self) {
-                self.channel.stop();
-            }
-        }
-
-        impl<PULL> TransferPayload for SpiRxDma<$SPIi, $RCi, PULL> {
-            fn start(&mut self) {
-                self.channel.start();
-            }
-            fn stop(&mut self) {
-                self.channel.stop();
-            }
-        }
-
-        impl<PULL> TransferPayload for SpiRxTxDma<$SPIi, $RCi, $TCi, PULL> {
-            fn start(&mut self) {
-                self.rxchannel.start();
-                self.txchannel.start();
-            }
-            fn stop(&mut self) {
-                self.txchannel.stop();
-                self.rxchannel.stop();
-            }
-        }
-
-        impl<B, PULL> crate::dma::ReadDma<B, u8> for SpiRxDma<$SPIi, $RCi, PULL>
-        where
-            B: WriteBuffer<Word = u8>,
-        {
-            fn read(mut self, mut buffer: B) -> Transfer<dma::W, B, Self> {
-                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
-                // until the end of the transfer.
-                let (ptr, len) = unsafe { buffer.write_buffer() };
-                self.channel.set_peripheral_address(
-                    unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-                self.channel.set_memory_address(ptr as u32, true);
-                self.channel.set_transfer_length(len);
-
-                atomic::compiler_fence(Ordering::Release);
-                self.channel.ch().cr().modify(|_, w| {
-                    // memory to memory mode disabled
-                    w.mem2mem().clear_bit();
-                    // medium channel priority level
-                    w.pl().medium();
-                    // 8-bit memory size
-                    w.msize().bits8();
-                    // 8-bit peripheral size
-                    w.psize().bits8();
-                    // circular mode disabled
-                    w.circ().clear_bit();
-                    // write to memory
-                    w.dir().clear_bit()
-                });
-                self.start();
-
-                Transfer::w(buffer, self)
-            }
-        }
-
-        impl<B, PULL> crate::dma::WriteDma<B, u8> for SpiTxDma<$SPIi, $TCi, PULL>
-        where
-            B: ReadBuffer<Word = u8>,
-        {
-            fn write(mut self, buffer: B) -> Transfer<dma::R, B, Self> {
-                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
-                // until the end of the transfer.
-                let (ptr, len) = unsafe { buffer.read_buffer() };
-                self.channel.set_peripheral_address(
-                    unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-                self.channel.set_memory_address(ptr as u32, true);
-                self.channel.set_transfer_length(len);
-
-                atomic::compiler_fence(Ordering::Release);
-                self.channel.ch().cr().modify(|_, w| {
-                    // memory to memory mode disabled
-                    w.mem2mem().clear_bit();
-                    // medium channel priority level
-                    w.pl().medium();
-                    // 8-bit memory size
-                    w.msize().bits8();
-                    // 8-bit peripheral size
-                    w.psize().bits8();
-                    // circular mode disabled
-                    w.circ().clear_bit();
-                    // read from memory
-                    w.dir().set_bit()
-                });
-                self.start();
-
-                Transfer::r(buffer, self)
-            }
-        }
-
-        impl<RXB, TXB, PULL> crate::dma::ReadWriteDma<RXB, TXB, u8>
-            for SpiRxTxDma<$SPIi, $RCi, $TCi, PULL>
-        where
-            RXB: WriteBuffer<Word = u8>,
-            TXB: ReadBuffer<Word = u8>,
-        {
-            fn read_write(
-                mut self,
-                mut rxbuffer: RXB,
-                txbuffer: TXB,
-            ) -> Transfer<dma::W, (RXB, TXB), Self> {
-                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
-                // until the end of the transfer.
-                let (rxptr, rxlen) = unsafe { rxbuffer.write_buffer() };
-                let (txptr, txlen) = unsafe { txbuffer.read_buffer() };
-
-                if rxlen != txlen {
-                    panic!("receive and send buffer lengths do not match!");
-                }
-
-                self.rxchannel.set_peripheral_address(
-                    unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-                self.rxchannel.set_memory_address(rxptr as u32, true);
-                self.rxchannel.set_transfer_length(rxlen);
-
-                self.txchannel.set_peripheral_address(
-                    unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-                self.txchannel.set_memory_address(txptr as u32, true);
-                self.txchannel.set_transfer_length(txlen);
-
-                atomic::compiler_fence(Ordering::Release);
-                self.rxchannel.ch().cr().modify(|_, w| {
-                    // memory to memory mode disabled
-                    w.mem2mem().clear_bit();
-                    // medium channel priority level
-                    w.pl().medium();
-                    // 8-bit memory size
-                    w.msize().bits8();
-                    // 8-bit peripheral size
-                    w.psize().bits8();
-                    // circular mode disabled
-                    w.circ().clear_bit();
-                    // write to memory
-                    w.dir().clear_bit()
-                });
-                self.txchannel.ch().cr().modify(|_, w| {
-                    // memory to memory mode disabled
-                    w.mem2mem().clear_bit();
-                    // medium channel priority level
-                    w.pl().medium();
-                    // 8-bit memory size
-                    w.msize().bits8();
-                    // 8-bit peripheral size
-                    w.psize().bits8();
-                    // circular mode disabled
-                    w.circ().clear_bit();
-                    // read from memory
-                    w.dir().set_bit()
-                });
-                self.start();
-
-                Transfer::w((rxbuffer, txbuffer), self)
-            }
-        }
-
-        pub type $slaverxdma<Otype = PushPull, PULL = Floating> =
-            SpiSlaveRxDma<$SPIi, $RCi, Otype, PULL>;
-        pub type $slavetxdma<Otype = PushPull, PULL = Floating> =
-            SpiSlaveTxDma<$SPIi, $TCi, Otype, PULL>;
-        pub type $slaverxtxdma<Otype = PushPull, PULL = Floating> =
-            SpiSlaveRxTxDma<$SPIi, $RCi, $TCi, Otype, PULL>;
-
-        impl<Otype, PULL> Transmit for SpiSlaveTxDma<$SPIi, $TCi, Otype, PULL> {
-            type TxChannel = $TCi;
-            type ReceivedWord = u8;
-        }
-
-        impl<Otype, PULL> Receive for SpiSlaveRxDma<$SPIi, $RCi, Otype, PULL> {
-            type RxChannel = $RCi;
-            type TransmittedWord = u8;
-        }
-
-        impl<Otype, PULL> Transmit for SpiSlaveRxTxDma<$SPIi, $RCi, $TCi, Otype, PULL> {
-            type TxChannel = $TCi;
-            type ReceivedWord = u8;
-        }
-
-        impl<Otype, PULL> Receive for SpiSlaveRxTxDma<$SPIi, $RCi, $TCi, Otype, PULL> {
-            type RxChannel = $RCi;
-            type TransmittedWord = u8;
-        }
-
-        impl<Otype, PULL> SpiSlave<$SPIi, u8, Otype, PULL> {
-            pub fn with_tx_dma(self, channel: $TCi) -> SpiSlaveTxDma<$SPIi, $TCi, Otype, PULL> {
-                self.spi.cr2().modify(|_, w| w.txdmaen().set_bit());
-                SpiSlaveTxDma {
-                    payload: self,
-                    channel,
-                }
-            }
-            pub fn with_rx_dma(self, channel: $RCi) -> SpiSlaveRxDma<$SPIi, $RCi, Otype, PULL> {
-                self.spi.cr2().modify(|_, w| w.rxdmaen().set_bit());
-                SpiSlaveRxDma {
-                    payload: self,
-                    channel,
-                }
-            }
-            pub fn with_rx_tx_dma(
-                self,
-                rxchannel: $RCi,
-                txchannel: $TCi,
-            ) -> SpiSlaveRxTxDma<$SPIi, $RCi, $TCi, Otype, PULL> {
-                self.spi
-                    .cr2()
-                    .modify(|_, w| w.rxdmaen().set_bit().txdmaen().set_bit());
-                SpiSlaveRxTxDma {
-                    payload: self,
-                    rxchannel,
-                    txchannel,
-                }
-            }
-        }
-
-        impl<Otype, PULL> SpiSlaveTxDma<$SPIi, $TCi, Otype, PULL> {
-            pub fn release(self) -> (SpiSlave<$SPIi, u8, Otype, PULL>, $TCi) {
-                let SpiSlaveTxDma { payload, channel } = self;
-                payload.spi.cr2().modify(|_, w| w.txdmaen().clear_bit());
-                (payload, channel)
-            }
-        }
-
-        impl<Otype, PULL> SpiSlaveRxDma<$SPIi, $RCi, Otype, PULL> {
-            pub fn release(self) -> (SpiSlave<$SPIi, u8, Otype, PULL>, $RCi) {
-                let SpiSlaveRxDma { payload, channel } = self;
-                payload.spi.cr2().modify(|_, w| w.rxdmaen().clear_bit());
-                (payload, channel)
-            }
-        }
-
-        impl<Otype, PULL> SpiSlaveRxTxDma<$SPIi, $RCi, $TCi, Otype, PULL> {
-            pub fn release(self) -> (SpiSlave<$SPIi, u8, Otype, PULL>, $RCi, $TCi) {
-                let SpiSlaveRxTxDma {
-                    payload,
-                    rxchannel,
-                    txchannel,
-                } = self;
-                payload
-                    .spi
-                    .cr2()
-                    .modify(|_, w| w.rxdmaen().clear_bit().txdmaen().clear_bit());
-                (payload, rxchannel, txchannel)
-            }
-        }
-
-        impl<Otype, PULL> TransferPayload for SpiSlaveTxDma<$SPIi, $TCi, Otype, PULL> {
-            fn start(&mut self) {
-                self.channel.start();
-            }
-            fn stop(&mut self) {
-                self.channel.stop();
-            }
-        }
-
-        impl<Otype, PULL> TransferPayload for SpiSlaveRxDma<$SPIi, $RCi, Otype, PULL> {
-            fn start(&mut self) {
-                self.channel.start();
-            }
-            fn stop(&mut self) {
-                self.channel.stop();
-            }
-        }
-
-        impl<Otype, PULL> TransferPayload for SpiSlaveRxTxDma<$SPIi, $RCi, $TCi, Otype, PULL> {
-            fn start(&mut self) {
-                self.rxchannel.start();
-                self.txchannel.start();
-            }
-            fn stop(&mut self) {
-                self.txchannel.stop();
-                self.rxchannel.stop();
-            }
-        }
-
-        impl<B, Otype, PULL> crate::dma::ReadDma<B, u8> for SpiSlaveRxDma<$SPIi, $RCi, Otype, PULL>
-        where
-            B: WriteBuffer<Word = u8>,
-        {
-            fn read(mut self, mut buffer: B) -> Transfer<dma::W, B, Self> {
-                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
-                // until the end of the transfer.
-                let (ptr, len) = unsafe { buffer.write_buffer() };
-                self.channel.set_peripheral_address(
-                    unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-                self.channel.set_memory_address(ptr as u32, true);
-                self.channel.set_transfer_length(len);
-
-                atomic::compiler_fence(Ordering::Release);
-                self.channel.ch().cr().modify(|_, w| {
-                    // memory to memory mode disabled
-                    w.mem2mem().clear_bit();
-                    // medium channel priority level
-                    w.pl().medium();
-                    // 8-bit memory size
-                    w.msize().bits8();
-                    // 8-bit peripheral size
-                    w.psize().bits8();
-                    // circular mode disabled
-                    w.circ().clear_bit();
-                    // write to memory
-                    w.dir().clear_bit()
-                });
-                self.start();
-
-                Transfer::w(buffer, self)
-            }
-        }
-
-        impl<B, Otype, PULL> crate::dma::WriteDma<B, u8> for SpiSlaveTxDma<$SPIi, $TCi, Otype, PULL>
-        where
-            B: ReadBuffer<Word = u8>,
-        {
-            fn write(mut self, buffer: B) -> Transfer<dma::R, B, Self> {
-                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
-                // until the end of the transfer.
-                let (ptr, len) = unsafe { buffer.read_buffer() };
-                self.channel.set_peripheral_address(
-                    unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-                self.channel.set_memory_address(ptr as u32, true);
-                self.channel.set_transfer_length(len);
-
-                atomic::compiler_fence(Ordering::Release);
-                self.channel.ch().cr().modify(|_, w| {
-                    // memory to memory mode disabled
-                    w.mem2mem().clear_bit();
-                    // medium channel priority level
-                    w.pl().medium();
-                    // 8-bit memory size
-                    w.msize().bits8();
-                    // 8-bit peripheral size
-                    w.psize().bits8();
-                    // circular mode disabled
-                    w.circ().clear_bit();
-                    // read from memory
-                    w.dir().set_bit()
-                });
-                self.start();
-
-                Transfer::r(buffer, self)
-            }
-        }
-
-        impl<RXB, TXB, Otype, PULL> crate::dma::ReadWriteDma<RXB, TXB, u8>
-            for SpiSlaveRxTxDma<$SPIi, $RCi, $TCi, Otype, PULL>
-        where
-            RXB: WriteBuffer<Word = u8>,
-            TXB: ReadBuffer<Word = u8>,
-        {
-            fn read_write(
-                mut self,
-                mut rxbuffer: RXB,
-                txbuffer: TXB,
-            ) -> Transfer<dma::W, (RXB, TXB), Self> {
-                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
-                // until the end of the transfer.
-                let (rxptr, rxlen) = unsafe { rxbuffer.write_buffer() };
-                let (txptr, txlen) = unsafe { txbuffer.read_buffer() };
-
-                if rxlen != txlen {
-                    panic!("receive and send buffer lengths do not match!");
-                }
-
-                self.rxchannel.set_peripheral_address(
-                    unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-                self.rxchannel.set_memory_address(rxptr as u32, true);
-                self.rxchannel.set_transfer_length(rxlen);
-
-                self.txchannel.set_peripheral_address(
-                    unsafe { (*<$SPIi>::ptr()).dr().as_ptr() as u32 },
-                    false,
-                );
-                self.txchannel.set_memory_address(txptr as u32, true);
-                self.txchannel.set_transfer_length(txlen);
-
-                atomic::compiler_fence(Ordering::Release);
-                self.rxchannel.ch().cr().modify(|_, w| {
-                    // memory to memory mode disabled
-                    w.mem2mem().clear_bit();
-                    // medium channel priority level
-                    w.pl().medium();
-                    // 8-bit memory size
-                    w.msize().bits8();
-                    // 8-bit peripheral size
-                    w.psize().bits8();
-                    // circular mode disabled
-                    w.circ().clear_bit();
-                    // write to memory
-                    w.dir().clear_bit()
-                });
-                self.txchannel.ch().cr().modify(|_, w| {
-                    // memory to memory mode disabled
-                    w.mem2mem().clear_bit();
-                    // medium channel priority level
-                    w.pl().medium();
-                    // 8-bit memory size
-                    w.msize().bits8();
-                    // 8-bit peripheral size
-                    w.psize().bits8();
-                    // circular mode disabled
-                    w.circ().clear_bit();
-                    // read from memory
-                    w.dir().set_bit()
-                });
-                self.start();
-
-                Transfer::w((rxbuffer, txbuffer), self)
-            }
-        }
-    };
-}
-
-spi_dma!(
-    pac::SPI1,
-    rx: dma1::C2,
-    tx: dma1::C3,
-    Spi1RxDma,
-    Spi1TxDma,
-    Spi1RxTxDma,
-    SpiSlave1RxDma,
-    SpiSlave1TxDma,
-    SpiSlave1RxTxDma
-);
-spi_dma!(
-    pac::SPI2,
-    rx: dma1::C4,
-    tx: dma1::C5,
-    Spi2RxDma,
-    Spi2TxDma,
-    Spi2RxTxDma,
-    SpiSlave2RxDma,
-    SpiSlave2TxDma,
-    SpiSlave2RxTxDma
-);
-#[cfg(feature = "connectivity")]
-spi_dma!(
-    pac::SPI3,
-    rx: dma2::C1,
-    tx: dma2::C2,
-    Spi3RxDma,
-    Spi3TxDma,
-    Spi3RxTxDma,
-    SpiSlave3RxDma,
-    SpiSlave3TxDma,
-    SpiSlave3RxTxDma
-);
diff --git a/src/spi/dma.rs b/src/spi/dma.rs
new file mode 100644
index 00000000..7b66e106
--- /dev/null
+++ b/src/spi/dma.rs
@@ -0,0 +1,366 @@
+use super::*;
+
+#[cfg(feature = "connectivity")]
+use crate::dma::dma2;
+use crate::dma::{self, Receive, RxDma, RxTxDma, Transfer, TransferPayload, Transmit, TxDma};
+use crate::dma::{dma1, Ch, DmaExt};
+
+pub type SpiTxDma<SPI, CHANNEL, PULL = Floating> = TxDma<Spi<SPI, u8, PULL>, CHANNEL>;
+pub type SpiRxDma<SPI, CHANNEL, PULL = Floating> = RxDma<Spi<SPI, u8, PULL>, CHANNEL>;
+pub type SpiRxTxDma<SPI, RXCHANNEL, TXCHANNEL, PULL = Floating> =
+    RxTxDma<Spi<SPI, u8, PULL>, RXCHANNEL, TXCHANNEL>;
+
+pub type SpiSlaveTxDma<SPI, CHANNEL, Otype, PULL = Floating> =
+    TxDma<SpiSlave<SPI, u8, Otype, PULL>, CHANNEL>;
+pub type SpiSlaveRxDma<SPI, CHANNEL, Otype, PULL = Floating> =
+    RxDma<SpiSlave<SPI, u8, Otype, PULL>, CHANNEL>;
+pub type SpiSlaveRxTxDma<SPI, RXCHANNEL, TXCHANNEL, Otype, PULL = Floating> =
+    RxTxDma<SpiSlave<SPI, u8, Otype, PULL>, RXCHANNEL, TXCHANNEL>;
+
+macro_rules! spi_impl {
+    ($Spi:ident) => {
+        impl<SPI: Instance, PULL, DMA: DmaExt, const C: u8> TransferPayload
+            for RxDma<$Spi<SPI, u8, PULL>, Ch<DMA, C>>
+        {
+            fn start(&mut self) {
+                self.channel.start();
+            }
+            fn stop(&mut self) {
+                self.channel.stop();
+            }
+        }
+
+        impl<SPI: Instance, PULL, DMA: DmaExt, const C: u8> TransferPayload
+            for TxDma<$Spi<SPI, u8, PULL>, Ch<DMA, C>>
+        {
+            fn start(&mut self) {
+                self.channel.start();
+            }
+            fn stop(&mut self) {
+                self.channel.stop();
+            }
+        }
+
+        impl<SPI: Instance, PULL, DMA1: DmaExt, const C1: u8, DMA2: DmaExt, const C2: u8>
+            TransferPayload for RxTxDma<$Spi<SPI, u8, PULL>, Ch<DMA1, C1>, Ch<DMA2, C2>>
+        {
+            fn start(&mut self) {
+                self.rxchannel.start();
+                self.txchannel.start();
+            }
+            fn stop(&mut self) {
+                self.txchannel.stop();
+                self.rxchannel.stop();
+            }
+        }
+
+        impl<SPI: Instance, PULL, CH> $Spi<SPI, u8, PULL>
+        where
+            Self: Transmit<TxChannel = CH>,
+        {
+            pub fn with_tx_dma(self, channel: CH) -> TxDma<$Spi<SPI, u8, PULL>, CH> {
+                self.spi.cr2().modify(|_, w| w.txdmaen().set_bit());
+                TxDma {
+                    payload: self,
+                    channel,
+                }
+            }
+        }
+        impl<SPI: Instance, PULL, CH> $Spi<SPI, u8, PULL>
+        where
+            Self: Receive<RxChannel = CH>,
+        {
+            pub fn with_rx_dma(self, channel: CH) -> RxDma<$Spi<SPI, u8, PULL>, CH> {
+                self.spi.cr2().modify(|_, w| w.rxdmaen().set_bit());
+                RxDma {
+                    payload: self,
+                    channel,
+                }
+            }
+        }
+        impl<SPI: Instance, PULL, RXCH, TXCH> $Spi<SPI, u8, PULL>
+        where
+            Self: Receive<RxChannel = RXCH>,
+            Self: Transmit<TxChannel = TXCH>,
+        {
+            pub fn with_rx_tx_dma(
+                self,
+                rxchannel: RXCH,
+                txchannel: TXCH,
+            ) -> RxTxDma<$Spi<SPI, u8, PULL>, RXCH, TXCH> {
+                self.spi
+                    .cr2()
+                    .modify(|_, w| w.rxdmaen().set_bit().txdmaen().set_bit());
+                RxTxDma {
+                    payload: self,
+                    rxchannel,
+                    txchannel,
+                }
+            }
+        }
+
+        impl<SPI: Instance, PULL, CH> TxDma<$Spi<SPI, u8, PULL>, CH> {
+            pub fn release(self) -> ($Spi<SPI, u8, PULL>, CH) {
+                // self.stop(); ?
+                self.payload
+                    .spi
+                    .cr2()
+                    .modify(|_, w| w.txdmaen().clear_bit());
+                (self.payload, self.channel)
+            }
+        }
+
+        impl<SPI: Instance, PULL, CH> RxDma<$Spi<SPI, u8, PULL>, CH> {
+            pub fn release(self) -> ($Spi<SPI, u8, PULL>, CH) {
+                // self.stop(); ?
+                self.payload
+                    .spi
+                    .cr2()
+                    .modify(|_, w| w.rxdmaen().clear_bit());
+                (self.payload, self.channel)
+            }
+        }
+
+        impl<SPI: Instance, PULL, RXCH, TXCH> RxTxDma<$Spi<SPI, u8, PULL>, RXCH, TXCH> {
+            pub fn release(self) -> ($Spi<SPI, u8, PULL>, RXCH, TXCH) {
+                // self.stop(); ?
+                self.payload
+                    .spi
+                    .cr2()
+                    .modify(|_, w| w.rxdmaen().clear_bit().txdmaen().clear_bit());
+                (self.payload, self.rxchannel, self.txchannel)
+            }
+        }
+
+        impl<SPI: Instance, PULL, DMA: DmaExt, const C: u8, B> crate::dma::ReadDma<B, u8>
+            for RxDma<$Spi<SPI, u8, PULL>, Ch<DMA, C>>
+        where
+            $Spi<SPI, u8, PULL>: Receive<RxChannel = Ch<DMA, C>>,
+            B: WriteBuffer<Word = u8>,
+        {
+            fn read(mut self, mut buffer: B) -> Transfer<dma::W, B, Self> {
+                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
+                // until the end of the transfer.
+                let (ptr, len) = unsafe { buffer.write_buffer() };
+                self.channel
+                    .set_peripheral_address(unsafe { (*SPI::ptr()).dr().as_ptr() as u32 }, false);
+                self.channel.set_memory_address(ptr as u32, true);
+                self.channel.set_transfer_length(len);
+
+                atomic::compiler_fence(Ordering::Release);
+                self.channel.ch().cr().modify(|_, w| {
+                    // memory to memory mode disabled
+                    w.mem2mem().clear_bit();
+                    // medium channel priority level
+                    w.pl().medium();
+                    // 8-bit memory size
+                    w.msize().bits8();
+                    // 8-bit peripheral size
+                    w.psize().bits8();
+                    // circular mode disabled
+                    w.circ().clear_bit();
+                    // write to memory
+                    w.dir().clear_bit()
+                });
+                self.start();
+
+                Transfer::w(buffer, self)
+            }
+        }
+
+        impl<SPI: Instance, PULL, DMA: DmaExt, const C: u8, B> crate::dma::WriteDma<B, u8>
+            for TxDma<$Spi<SPI, u8, PULL>, Ch<DMA, C>>
+        where
+            $Spi<SPI, u8, PULL>: Transmit<TxChannel = Ch<DMA, C>>,
+            B: ReadBuffer<Word = u8>,
+        {
+            fn write(mut self, buffer: B) -> Transfer<dma::R, B, Self> {
+                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
+                // until the end of the transfer.
+                let (ptr, len) = unsafe { buffer.read_buffer() };
+                self.channel
+                    .set_peripheral_address(unsafe { (*SPI::ptr()).dr().as_ptr() as u32 }, false);
+                self.channel.set_memory_address(ptr as u32, true);
+                self.channel.set_transfer_length(len);
+
+                atomic::compiler_fence(Ordering::Release);
+                self.channel.ch().cr().modify(|_, w| {
+                    // memory to memory mode disabled
+                    w.mem2mem().clear_bit();
+                    // medium channel priority level
+                    w.pl().medium();
+                    // 8-bit memory size
+                    w.msize().bits8();
+                    // 8-bit peripheral size
+                    w.psize().bits8();
+                    // circular mode disabled
+                    w.circ().clear_bit();
+                    // read from memory
+                    w.dir().set_bit()
+                });
+                self.start();
+
+                Transfer::r(buffer, self)
+            }
+        }
+
+        impl<
+                SPI: Instance,
+                PULL,
+                RXDMA: DmaExt,
+                const RXC: u8,
+                RXB,
+                TXDMA: DmaExt,
+                const TXC: u8,
+                TXB,
+            > crate::dma::ReadWriteDma<RXB, TXB, u8>
+            for RxTxDma<$Spi<SPI, u8, PULL>, Ch<RXDMA, RXC>, Ch<TXDMA, TXC>>
+        where
+            $Spi<SPI, u8, PULL>:
+                Receive<RxChannel = Ch<RXDMA, RXC>> + Transmit<TxChannel = Ch<TXDMA, TXC>>,
+            RXB: WriteBuffer<Word = u8>,
+            TXB: ReadBuffer<Word = u8>,
+        {
+            fn read_write(
+                mut self,
+                mut rxbuffer: RXB,
+                txbuffer: TXB,
+            ) -> Transfer<dma::W, (RXB, TXB), Self> {
+                // NOTE(unsafe) We own the buffer now and we won't call other `&mut` on it
+                // until the end of the transfer.
+                let (rxptr, rxlen) = unsafe { rxbuffer.write_buffer() };
+                let (txptr, txlen) = unsafe { txbuffer.read_buffer() };
+
+                if rxlen != txlen {
+                    panic!("receive and send buffer lengths do not match!");
+                }
+
+                self.rxchannel
+                    .set_peripheral_address(unsafe { (*SPI::ptr()).dr().as_ptr() as u32 }, false);
+                self.rxchannel.set_memory_address(rxptr as u32, true);
+                self.rxchannel.set_transfer_length(rxlen);
+
+                self.txchannel
+                    .set_peripheral_address(unsafe { (*SPI::ptr()).dr().as_ptr() as u32 }, false);
+                self.txchannel.set_memory_address(txptr as u32, true);
+                self.txchannel.set_transfer_length(txlen);
+
+                atomic::compiler_fence(Ordering::Release);
+                self.rxchannel.ch().cr().modify(|_, w| {
+                    // memory to memory mode disabled
+                    w.mem2mem().clear_bit();
+                    // medium channel priority level
+                    w.pl().medium();
+                    // 8-bit memory size
+                    w.msize().bits8();
+                    // 8-bit peripheral size
+                    w.psize().bits8();
+                    // circular mode disabled
+                    w.circ().clear_bit();
+                    // write to memory
+                    w.dir().clear_bit()
+                });
+                self.txchannel.ch().cr().modify(|_, w| {
+                    // memory to memory mode disabled
+                    w.mem2mem().clear_bit();
+                    // medium channel priority level
+                    w.pl().medium();
+                    // 8-bit memory size
+                    w.msize().bits8();
+                    // 8-bit peripheral size
+                    w.psize().bits8();
+                    // circular mode disabled
+                    w.circ().clear_bit();
+                    // read from memory
+                    w.dir().set_bit()
+                });
+                self.start();
+
+                Transfer::w((rxbuffer, txbuffer), self)
+            }
+        }
+    };
+}
+
+spi_impl!(Spi);
+spi_impl!(SpiSlave);
+
+macro_rules! spi_dma {
+    (
+        $SPIi:ty,
+        rx: $RCi:ty,
+        tx: $TCi:ty,
+        $rxdma:ident,
+        $txdma:ident,
+        $rxtxdma:ident,
+        $slaverxdma:ident,
+        $slavetxdma:ident,
+        $slaverxtxdma:ident
+    ) => {
+        pub type $rxdma<PULL = Floating> = SpiRxDma<$SPIi, $RCi, PULL>;
+        pub type $txdma<PULL = Floating> = SpiTxDma<$SPIi, $TCi, PULL>;
+        pub type $rxtxdma<PULL = Floating> = SpiRxTxDma<$SPIi, $RCi, $TCi, PULL>;
+
+        impl<PULL> Transmit for Spi<$SPIi, u8, PULL> {
+            type TxChannel = $TCi;
+            type ReceivedWord = u8;
+        }
+
+        impl<PULL> Receive for Spi<$SPIi, u8, PULL> {
+            type RxChannel = $RCi;
+            type TransmittedWord = u8;
+        }
+
+        pub type $slaverxdma<Otype = PushPull, PULL = Floating> =
+            SpiSlaveRxDma<$SPIi, $RCi, Otype, PULL>;
+        pub type $slavetxdma<Otype = PushPull, PULL = Floating> =
+            SpiSlaveTxDma<$SPIi, $TCi, Otype, PULL>;
+        pub type $slaverxtxdma<Otype = PushPull, PULL = Floating> =
+            SpiSlaveRxTxDma<$SPIi, $RCi, $TCi, Otype, PULL>;
+
+        impl<Otype, PULL> Transmit for SpiSlave<$SPIi, u8, Otype, PULL> {
+            type TxChannel = $TCi;
+            type ReceivedWord = u8;
+        }
+
+        impl<Otype, PULL> Receive for SpiSlave<$SPIi, u8, Otype, PULL> {
+            type RxChannel = $RCi;
+            type TransmittedWord = u8;
+        }
+    };
+}
+
+spi_dma!(
+    pac::SPI1,
+    rx: dma1::C2,
+    tx: dma1::C3,
+    Spi1RxDma,
+    Spi1TxDma,
+    Spi1RxTxDma,
+    SpiSlave1RxDma,
+    SpiSlave1TxDma,
+    SpiSlave1RxTxDma
+);
+spi_dma!(
+    pac::SPI2,
+    rx: dma1::C4,
+    tx: dma1::C5,
+    Spi2RxDma,
+    Spi2TxDma,
+    Spi2RxTxDma,
+    SpiSlave2RxDma,
+    SpiSlave2TxDma,
+    SpiSlave2RxTxDma
+);
+#[cfg(feature = "connectivity")]
+spi_dma!(
+    pac::SPI3,
+    rx: dma2::C1,
+    tx: dma2::C2,
+    Spi3RxDma,
+    Spi3TxDma,
+    Spi3RxTxDma,
+    SpiSlave3RxDma,
+    SpiSlave3TxDma,
+    SpiSlave3RxTxDma
+);
diff --git a/src/time.rs b/src/time.rs
index b76087e2..74ca82a9 100644
--- a/src/time.rs
+++ b/src/time.rs
@@ -35,7 +35,8 @@ use cortex_m::peripheral::{DCB, DWT};
 use crate::rcc::Clocks;
 
 /// Bits per second
-#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
+#[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct Bps(pub u32);
 
 pub use fugit::{