treewide: use PTR instead of ptr()

Author: newAM

hal/src/adc.rs

@@ -847,7 +847,7 @@ impl Adc {
     #[inline]
     pub fn isr() -> pac::adc::isr::R {
         // saftey: atomic read with no side-effects
-        unsafe { (*pac::ADC::ptr()).isr.read() }
+        unsafe { (*pac::ADC::PTR).isr.read() }
     }
 
     /// Enable and disable interrupts.

hal/src/gpio.rs

@@ -440,9 +440,9 @@ pub trait Exti {
 pub mod pins {
     // Switch to this when avaliable on stable
     // https://github.com/rust-lang/rust/issues/51910
-    // const GPIOA_BASE: usize = pac::GPIOA::ptr() as *const _ as usize;
-    // const GPIOB_BASE: usize = pac::GPIOB::ptr() as *const _ as usize;
-    // const GPIOC_BASE: usize = pac::GPIOC::ptr() as *const _ as usize;
+    // const GPIOA_BASE: usize = pac::GPIOA::PTR as *const _ as usize;
+    // const GPIOB_BASE: usize = pac::GPIOB::PTR as *const _ as usize;
+    // const GPIOC_BASE: usize = pac::GPIOC::PTR as *const _ as usize;
 
     const GPIOA_BASE: usize = 0x4800_0000;
     const GPIOB_BASE: usize = 0x4800_0400;
@@ -752,7 +752,7 @@ pub mod pins {
                     #[inline]
                     fn clear_exti() {
                         // safety: atomic write with no side effects
-                        unsafe { (*pac::EXTI::ptr()).pr1.write(|w| w.[<pif $n>]().set_bit()) }
+                        unsafe { (*pac::EXTI::PTR).pr1.write(|w| w.[<pif $n>]().set_bit()) }
                     }
                 }
             }

hal/src/lptim/mod.rs

@@ -122,7 +122,7 @@ macro_rules! impl_lptim_base_for {
             #[inline(always)]
             fn isr() -> u32 {
                 // safety: atomic read with no side effects
-                unsafe { (*pac::$lptim::ptr()).isr.read().bits() }
+                unsafe { (*pac::$lptim::PTR).isr.read().bits() }
             }
 
             #[inline(always)]
@@ -181,7 +181,7 @@ macro_rules! impl_lptim_base_for {
             /// is set.
             #[inline(always)]
             unsafe fn cnt() -> u16 {
-                (*pac::$lptim::ptr()).cnt.read().cnt().bits()
+                (*pac::$lptim::PTR).cnt.read().cnt().bits()
             }
 
             #[inline(always)]

hal/src/rtc.rs

@@ -211,14 +211,14 @@ impl Rtc {
     #[inline]
     pub fn status() -> pac::rtc::sr::R {
         // saftey: atomic read with no side-effects
-        unsafe { (*pac::RTC::ptr()).sr.read() }
+        unsafe { (*pac::RTC::PTR).sr.read() }
     }
 
     /// Read the RTC masked status (interrupt) register.
     #[inline]
     pub fn masked_status() -> pac::rtc::misr::R {
         // saftey: atomic read with no side-effects
-        unsafe { (*pac::RTC::ptr()).misr.read() }
+        unsafe { (*pac::RTC::PTR).misr.read() }
     }
 
     /// Clear status (interrupt) flags.
@@ -227,7 +227,7 @@ impl Rtc {
     #[inline]
     pub fn clear_status(mask: u32) {
         // safety: mask is masked with valid register fields
-        unsafe { (*pac::RTC::ptr()).scr.write(|w| w.bits(mask & stat::ALL)) }
+        unsafe { (*pac::RTC::PTR).scr.write(|w| w.bits(mask & stat::ALL)) }
     }
 
     // configure prescaler for a 1Hz clock
@@ -282,7 +282,7 @@ impl Rtc {
     /// * Backup domain write protection is enabled.
     pub fn set_date_time(&mut self, date_time: chrono::NaiveDateTime) {
         // safety: atomic read with no side effects
-        assert!(unsafe { (*pac::PWR::ptr()).cr1.read().dbp().bit_is_set() });
+        assert!(unsafe { (*pac::PWR::PTR).cr1.read().dbp().bit_is_set() });
 
         // enter initialization mode
         self.rtc.icsr.modify(|_, w| w.init().init_mode());

hal/src/subghz/mod.rs

@@ -101,17 +101,13 @@ impl Nss {
     /// Clear NSS, enabling SPI transactions
     #[inline(always)]
     fn clear() {
-        unsafe {
-            (*pac::PWR::ptr())
-                .subghzspicr
-                .write(|w| w.nss().clear_bit())
-        }
+        unsafe { (*pac::PWR::PTR).subghzspicr.write(|w| w.nss().clear_bit()) }
     }
 
     /// Set NSS, disabling SPI transactions
     #[inline(always)]
     fn set() {
-        unsafe { (*pac::PWR::ptr()).subghzspicr.write(|w| w.nss().set_bit()) }
+        unsafe { (*pac::PWR::PTR).subghzspicr.write(|w| w.nss().set_bit()) }
     }
 }
 
@@ -193,7 +189,7 @@ pub fn mask_irq() {
 #[inline]
 pub fn rfbusys() -> bool {
     // safety: atmoic read with no side-effects
-    unsafe { (*pac::PWR::ptr()).sr2.read().rfbusys().is_busy() }
+    unsafe { (*pac::PWR::PTR).sr2.read().rfbusys().is_busy() }
 }
 
 /// Returns `true` if the radio is busy or NSS is low.
@@ -203,7 +199,7 @@ pub fn rfbusys() -> bool {
 #[inline]
 pub fn rfbusyms() -> bool {
     // saftey: atomic read with no side-effects
-    unsafe { (*pac::PWR::ptr()).sr2.read().rfbusyms().is_busy() }
+    unsafe { (*pac::PWR::PTR).sr2.read().rfbusyms().is_busy() }
 }
 
 /// Sub-GHz radio peripheral.