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41 | 41 |
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42 | 42 | /* Definition for BSP SD */ |
43 | 43 | #if defined(SDMMC1) || defined(SDMMC2) |
44 | | -#ifndef SD_INSTANCE |
45 | | -#define SD_INSTANCE SDMMC1 |
46 | | -#endif |
47 | | - |
48 | | -#define SD_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE |
49 | | -#define SD_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE |
50 | | -#ifdef SDMMC2 |
51 | | -#define SD_CLK2_ENABLE __HAL_RCC_SDMMC2_CLK_ENABLE |
52 | | -#define SD_CLK2_DISABLE __HAL_RCC_SDMMC2_CLK_DISABLE |
53 | | -#endif |
54 | | - |
55 | | -#define SD_CLK_EDGE SDMMC_CLOCK_EDGE_RISING |
56 | | -#define SD_CLK_BYPASS SDMMC_CLOCK_BYPASS_DISABLE |
57 | | -#define SD_CLK_PWR_SAVE SDMMC_CLOCK_POWER_SAVE_DISABLE |
58 | | -#define SD_BUS_WIDE_1B SDMMC_BUS_WIDE_1B |
59 | | -#define SD_BUS_WIDE_4B SDMMC_BUS_WIDE_4B |
60 | | -#define SD_BUS_WIDE_8B SDMMC_BUS_WIDE_8B |
61 | | -#define SD_HW_FLOW_CTRL_ENABLE SDMMC_HARDWARE_FLOW_CONTROL_ENABLE |
62 | | -#define SD_HW_FLOW_CTRL_DISABLE SDMMC_HARDWARE_FLOW_CONTROL_DISABLE |
63 | | - |
64 | | -#ifdef STM32H7xx |
65 | | -#define SD_CLK_DIV 1 |
66 | | -#else |
67 | | -#define SD_CLK_DIV SDMMC_TRANSFER_CLK_DIV |
68 | | -#endif |
69 | | - |
70 | | -#ifdef SDMMC_TRANSCEIVER_ENABLE |
71 | | -#define SD_TRANSCEIVER_ENABLE SDMMC_TRANSCEIVER_ENABLE |
72 | | -#define SD_TRANSCEIVER_DISABLE SDMMC_TRANSCEIVER_DISABLE |
73 | | -#endif |
| 44 | + #ifndef SD_INSTANCE |
| 45 | + #define SD_INSTANCE SDMMC1 |
| 46 | + #endif |
| 47 | + |
| 48 | + #define SD_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE |
| 49 | + #define SD_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE |
| 50 | + #ifdef SDMMC2 |
| 51 | + #define SD_CLK2_ENABLE __HAL_RCC_SDMMC2_CLK_ENABLE |
| 52 | + #define SD_CLK2_DISABLE __HAL_RCC_SDMMC2_CLK_DISABLE |
| 53 | + #endif |
| 54 | + |
| 55 | + #define SD_CLK_EDGE SDMMC_CLOCK_EDGE_RISING |
| 56 | + #define SD_CLK_BYPASS SDMMC_CLOCK_BYPASS_DISABLE |
| 57 | + #define SD_CLK_PWR_SAVE SDMMC_CLOCK_POWER_SAVE_DISABLE |
| 58 | + #define SD_BUS_WIDE_1B SDMMC_BUS_WIDE_1B |
| 59 | + #define SD_BUS_WIDE_4B SDMMC_BUS_WIDE_4B |
| 60 | + #define SD_BUS_WIDE_8B SDMMC_BUS_WIDE_8B |
| 61 | + #define SD_HW_FLOW_CTRL_ENABLE SDMMC_HARDWARE_FLOW_CONTROL_ENABLE |
| 62 | + #define SD_HW_FLOW_CTRL_DISABLE SDMMC_HARDWARE_FLOW_CONTROL_DISABLE |
| 63 | + |
| 64 | + #ifdef STM32H7xx |
| 65 | + #define SD_CLK_DIV 1 |
| 66 | + #else |
| 67 | + #define SD_CLK_DIV SDMMC_TRANSFER_CLK_DIV |
| 68 | + #endif |
| 69 | + |
| 70 | + #ifdef SDMMC_TRANSCEIVER_ENABLE |
| 71 | + #define SD_TRANSCEIVER_ENABLE SDMMC_TRANSCEIVER_ENABLE |
| 72 | + #define SD_TRANSCEIVER_DISABLE SDMMC_TRANSCEIVER_DISABLE |
| 73 | + #endif |
74 | 74 |
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75 | 75 | #elif defined(SDIO) |
76 | | -#define SD_INSTANCE SDIO |
77 | | -#define SD_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE |
78 | | -#define SD_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE |
79 | | -#define SD_CLK_EDGE SDIO_CLOCK_EDGE_RISING |
80 | | -#define SD_CLK_BYPASS SDIO_CLOCK_BYPASS_DISABLE |
81 | | -#define SD_CLK_PWR_SAVE SDIO_CLOCK_POWER_SAVE_DISABLE |
82 | | -#define SD_BUS_WIDE_1B SDIO_BUS_WIDE_1B |
83 | | -#define SD_BUS_WIDE_4B SDIO_BUS_WIDE_4B |
84 | | -#define SD_BUS_WIDE_8B SDIO_BUS_WIDE_8B |
85 | | -#define SD_HW_FLOW_CTRL_ENABLE SDIO_HARDWARE_FLOW_CONTROL_ENABLE |
86 | | -#define SD_HW_FLOW_CTRL_DISABLE SDIO_HARDWARE_FLOW_CONTROL_DISABLE |
87 | | -#define SD_CLK_DIV SDIO_TRANSFER_CLK_DIV |
| 76 | + #define SD_INSTANCE SDIO |
| 77 | + #define SD_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE |
| 78 | + #define SD_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE |
| 79 | + #define SD_CLK_EDGE SDIO_CLOCK_EDGE_RISING |
| 80 | + #define SD_CLK_BYPASS SDIO_CLOCK_BYPASS_DISABLE |
| 81 | + #define SD_CLK_PWR_SAVE SDIO_CLOCK_POWER_SAVE_DISABLE |
| 82 | + #define SD_BUS_WIDE_1B SDIO_BUS_WIDE_1B |
| 83 | + #define SD_BUS_WIDE_4B SDIO_BUS_WIDE_4B |
| 84 | + #define SD_BUS_WIDE_8B SDIO_BUS_WIDE_8B |
| 85 | + #define SD_HW_FLOW_CTRL_ENABLE SDIO_HARDWARE_FLOW_CONTROL_ENABLE |
| 86 | + #define SD_HW_FLOW_CTRL_DISABLE SDIO_HARDWARE_FLOW_CONTROL_DISABLE |
| 87 | + #define SD_CLK_DIV SDIO_TRANSFER_CLK_DIV |
88 | 88 | #else |
89 | | -#error "Unknown SD_INSTANCE" |
| 89 | + #error "Unknown SD_INSTANCE" |
90 | 90 | #endif |
91 | 91 |
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92 | 92 | #ifndef SD_HW_FLOW_CTRL |
93 | | -#define SD_HW_FLOW_CTRL SD_HW_FLOW_CTRL_DISABLE |
| 93 | + #define SD_HW_FLOW_CTRL SD_HW_FLOW_CTRL_DISABLE |
94 | 94 | #endif |
95 | 95 |
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96 | 96 | #ifndef SD_BUS_WIDE |
97 | | -#define SD_BUS_WIDE SD_BUS_WIDE_4B |
| 97 | + #define SD_BUS_WIDE SD_BUS_WIDE_4B |
98 | 98 | #endif |
99 | 99 |
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100 | 100 | #if defined(SDMMC_TRANSCEIVER_ENABLE) && !defined(SD_TRANSCEIVER_MODE) |
101 | | -#define SD_TRANSCEIVER_MODE SD_TRANSCEIVER_DISABLE |
| 101 | + #define SD_TRANSCEIVER_MODE SD_TRANSCEIVER_DISABLE |
102 | 102 | #endif |
103 | 103 |
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104 | 104 | /* BSP SD Private Variables */ |
105 | 105 | static SD_HandleTypeDef uSdHandle; |
106 | 106 | static uint32_t SD_detect_ll_gpio_pin = LL_GPIO_PIN_ALL; |
107 | 107 | static GPIO_TypeDef *SD_detect_gpio_port = GPIOA; |
108 | 108 | #ifdef SDMMC_TRANSCEIVER_ENABLE |
109 | | -static uint32_t SD_trans_en_ll_gpio_pin = LL_GPIO_PIN_ALL; |
110 | | -static GPIO_TypeDef *SD_trans_en_gpio_port = GPIOA; |
111 | | -static uint32_t SD_trans_sel_ll_gpio_pin = LL_GPIO_PIN_ALL; |
112 | | -static GPIO_TypeDef *SD_trans_sel_gpio_port = GPIOA; |
| 109 | + static uint32_t SD_trans_en_ll_gpio_pin = LL_GPIO_PIN_ALL; |
| 110 | + static GPIO_TypeDef *SD_trans_en_gpio_port = GPIOA; |
| 111 | + static uint32_t SD_trans_sel_ll_gpio_pin = LL_GPIO_PIN_ALL; |
| 112 | + static GPIO_TypeDef *SD_trans_sel_gpio_port = GPIOA; |
113 | 113 | #endif |
114 | 114 | #ifndef STM32L1xx |
115 | | -#define SD_OK HAL_OK |
116 | | -#define SD_TRANSFER_OK ((uint8_t)0x00) |
117 | | -#define SD_TRANSFER_BUSY ((uint8_t)0x01) |
| 115 | + #define SD_OK HAL_OK |
| 116 | + #define SD_TRANSFER_OK ((uint8_t)0x00) |
| 117 | + #define SD_TRANSFER_BUSY ((uint8_t)0x01) |
118 | 118 | #else /* STM32L1xx */ |
119 | | -static SD_CardInfo uSdCardInfo; |
| 119 | + static SD_CardInfo uSdCardInfo; |
120 | 120 | #endif |
121 | 121 |
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122 | 122 |
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