peci: Actually clear ESUCTRL0 before starting

Bits 1 and 2 of the register are write-cleared.

Signed-off-by: Tim Crawford <tcrawford@system76.com>

Author: crawfxrd

src/board/system76/common/peci.c

@@ -63,7 +63,7 @@ void peci_init(void) {}
 bool peci_get_temp(int16_t *const data) {
     //TODO: Wait for completion?
     // Clear upstream status
-    ESUCTRL0 = ESUCTRL0;
+    ESUCTRL0 = ESUCTRL0_CH_DISABLED | ESUCTRL0_DONE;
     // Clear OOB status
     ESOCTRL0 = ESOCTRL0;
 
@@ -114,7 +114,7 @@ bool peci_get_temp(int16_t *const data) {
             return false;
         }
     }
-    // Clear upstream done status
+    // Clear upstream done status and disable initiating upstream transactions
     ESUCTRL0 = ESUCTRL0_DONE;
 
     // Wait for response
@@ -156,7 +156,7 @@ bool peci_get_temp(int16_t *const data) {
 int16_t peci_wr_pkg_config(uint8_t index, uint16_t param, uint32_t data) {
     //TODO: Wait for completion?
     // Clear upstream status
-    ESUCTRL0 = ESUCTRL0;
+    ESUCTRL0 = ESUCTRL0_CH_DISABLED | ESUCTRL0_DONE;
     // Clear OOB status
     ESOCTRL0 = ESOCTRL0;
 
@@ -221,7 +221,7 @@ int16_t peci_wr_pkg_config(uint8_t index, uint16_t param, uint32_t data) {
             return false;
         }
     }
-    // Clear upstream done status
+    // Clear upstream done status and disable initiating upstream transactions
     ESUCTRL0 = ESUCTRL0_DONE;
 
     // Wait for response

src/ec/ite/include/ec/espi.h

@@ -114,6 +114,7 @@ volatile uint8_t __xdata __at(0x31A3) ESGCTRL3;
 volatile uint8_t __xdata __at(0x31B0) ESUCTRL0;
 #define ESUCTRL0_ENABLE BIT(7)
 #define ESUCTRL0_GO BIT(6)
+#define ESUCTRL0_CH_DISABLED BIT(2)
 #define ESUCTRL0_DONE BIT(1)
 #define ESUCTRL0_BUSY BIT(0)