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## Setting up Your Environment
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If you cloned the repository you will need to set up the git submodules (if you downloaded and extracted a release, you can skip this step):
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git submodule init
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git submodule update
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VTR requires several system packages. From the top-level directory, run the following script to install the required packages on a modern Debian or Ubuntu system:
Copy file name to clipboardExpand all lines: README.developers.md
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QoR checks in this regression test are primarily 'canary' checks to catch gross degradations in QoR.
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Occasionally, changes can cause QoR failures (e.g. due to CAD noise -- particularly on small benchmarks); usually such failures are not a concern if the QoR differences are small.
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### vtr_reg_nightly_test1-3
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### vtr_reg_nightly_test1-N
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**Goal:**Basic QoR and Performance evaluation
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**Goal:**Most QoR and Performance evaluation
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**Feature Coverage:** Medium
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**Architectures:** A wider variety of architectures
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**Benchmarks:** Small-medium size, diverse. All include:
* Titan benchmarks except gaussian_blur (which has the longest run time)
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* Koios benchmarks
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* Various special benchmarks and tests for functionality
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QoR checks in these regression suites are aimed at evaluating quality and run-time of the VTR flow.
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As a result any QoR failures are a concern and should be investigated and understood.
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Note:
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These suites comproise a single large suite, `vtr_reg_nightly` and should be run together to test nightly level regression. They are mostly similar in benchmark coverage interms of size and diversity however each suite tests some unique benchmarks in addition to the VTR benchmarks.
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These suites comprise a single large suite, `vtr_reg_nightly` and should be run together to test nightly level regression. They are mostly similar in benchmark coverage interms of size and diversity however each suite tests some unique benchmarks in addition to the VTR benchmarks. Each vtr_reg_nightly<N> suite runs on a different server (in parallel), so by having N such test suites we speed up CI by a factor of N. Currently the runtime of each suite is capped at 6 hours, so if the runtime exceeds six hours a new vtr_reg_nightly suite (i.e. N+1) should be created.
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| suite | wall-clock time| Additional benchmarks|
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|-------|----------------|----------------------|
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|vtr_reg_nightly_test1|~4.5 hours with `-j8`|ISPD and MCNC20 |
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|vtr_reg_nightly_test2|~6 hours with `-j8`|Titan23 and Titan `other`|
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|vtr_reg_nightly_test3|~5.5 hours with `-j8`|none|
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### vtr_reg_weekly
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**Architectures:** A wide variety of architectures
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## Continuous integration (CI)
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For the following tests, you can use remote servers instead of running them locally. Once the changes are pushed into the
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remote repository, or a PR is created, the [Test Workflow](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/.github/workflows/test.yml)
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will be triggered. The following tests are included in the workflow:
# ABC: System for Sequential Logic Synthesis and Formal Verification
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ABC is always changing but the current snapshot is believed to be stable.
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ABC is always changing but the current snapshot is believed to be stable.
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## ABC fork with new features
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Here is a [fork](https://github.com/yongshiwo/abc.git) of ABC containing Agdmap, a novel technology mapper for LUT-based FPGAs. Agdmap is based on a technology mapping algorithm with adaptive gate decomposition [1]. It is a cut enumeration based mapping algorithm with bin packing for simultaneous wide gate decomposition, which is a patent pending technology.
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The mapper is developed and maintained by Longfei Fan and Prof. Chang Wu at Fudan University in Shanghai, China. The experimental results presented in [1] indicate that Agdmap can substantially improve area (by 10% or more) when compared against the best LUT mapping solutions in ABC, such as command "if".
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The source code is provided for research and evaluation only. For commercial usage, please contact Prof. Chang Wu at wuchang@fudan.edu.cn.
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References:
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[1] L. Fan and C. Wu, "FPGA technology mapping with adaptive gate decompostion", ACM/SIGDA FPGA International Symposium on FPGAs, 2023.
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## Compiling:
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To build the demo program
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* Copy demo.cc and libabc.a to the working directory
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* Copy demo.c and libabc.a to the working directory
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