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amin1377amin1377
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Merge branch 'master' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into fix_3d_arch
2 parents 8ae89e7 + 69f9ebe commit 7752573

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‎.github/workflows/test.yml‎

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- {test: "vtr_reg_nightly_test1", cores: "16", options: "", cmake: "", extra_pkgs: ""}
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- {test: "vtr_reg_nightly_test1_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
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- {test: "vtr_reg_nightly_test2", cores: "16", options: "", cmake: "", extra_pkgs: ""}
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- {test: "vtr_reg_nightly_test2_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: "" }
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- {test: "vtr_reg_nightly_test2_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
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- {test: "vtr_reg_nightly_test3", cores: "16", options: "", cmake: "", extra_pkgs: ""}
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- {test: "vtr_reg_nightly_test3_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
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- {test: "vtr_reg_nightly_test4", cores: "16", options: "", cmake: "", extra_pkgs: "" }
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- {test: "vtr_reg_nightly_test4_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: "" }
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- {test: "vtr_reg_nightly_test4", cores: "16", options: "", cmake: "", extra_pkgs: ""}
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- {test: "vtr_reg_nightly_test4_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
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- {test: "vtr_reg_nightly_test5", cores: "16", options: "", cmake: "", extra_pkgs: ""}
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- {test: "vtr_reg_nightly_test6", cores: "16", options: "", cmake: "", extra_pkgs: ""}
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- {test: "vtr_reg_nightly_test7", cores: "16", options: "", cmake: "", extra_pkgs: ""}
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- {test: "vtr_reg_parmys", cores: "16", options: "", cmake: "", extra_pkgs: "" }
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- {test: "vtr_reg_strong", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3", extra_pkgs: "libeigen3-dev"}
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- {test: "vtr_reg_strong_odin", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
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- {test: "vtr_reg_strong_odin", cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
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- {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
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- {test: "odin_reg_strong", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
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- {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
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env:
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DEBIAN_FRONTEND: "noninteractive"

‎README.developers.md‎

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‎libs/EXTERNAL/CMakeLists.txt‎

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GIT_REPOSITORY https://github.com/chipsalliance/Surelog.git
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GIT_TAG v1.71
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GIT_PROGRESS TRUE
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GIT_SHALLOW TRUE
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# setting source, build and install directories
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SOURCE_DIR "${SURELOG_SOURCE_DIR}"
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LOG_BUILD ON
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LOG_UPDATE ON
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LOG_INSTALL ON
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LOG_CONFIGURE ON
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LOG_CONFIGURE OFF
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LOG_OUTPUT_ON_FAILURE ON
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# dependency
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GIT_REPOSITORY https://github.com/chipsalliance/yosys-f4pga-plugins.git
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GIT_TAG v1.20230808
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GIT_PROGRESS TRUE
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GIT_SHALLOW TRUE
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# setting source, build and install directories
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SOURCE_DIR "${YOSYS_F4PGA_PLUGINS_SOURCE_DIR}"
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LOG_BUILD ON
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LOG_UPDATE ON
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LOG_INSTALL ON
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LOG_CONFIGURE ON
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LOG_CONFIGURE OFF
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LOG_OUTPUT_ON_FAILURE ON
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# dependency

‎odin_ii/regression_test/benchmark/suite/heavy_suite/task_list.conf‎

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regression_test/benchmark/task/full
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regression_test/benchmark/task/large
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regression_test/benchmark/task/koios
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regression_test/benchmark/suite/koios_nightly_suite
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regression_test/benchmark/suite/koios_weekly_suite

‎odin_ii/regression_test/benchmark/suite/koios_nightly_suite/task_list.conf‎

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regression_test/benchmark/task/koios/koios_medium
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regression_test/benchmark/task/koios/koios_medium_no_hb

‎odin_ii/regression_test/benchmark/suite/koios_weekly_suite/task_list.conf‎

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regression_test/benchmark/task/koios/koios_large
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‎odin_ii/regression_test/benchmark/suite/light_suite/task_list.conf‎

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regression_test/benchmark/task/FIR
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regression_test/benchmark/suite/complex_synthesis_suite
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regression_test/benchmark/suite/vtr_multiclock_suite
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regression_test/benchmark/suite/vtr_multiclock_suite

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