Sort netlists according to block traversal ordering

edg/electronics_model/NetlistGenerator.py

@@ -82,12 +82,15 @@ def __init__(self, design: CompiledDesign):
         self.all_scopes = [BoardScope.empty(TransformUtil.Path.empty())]  # list of unique scopes
         self.scopes: Scopes = {TransformUtil.Path.empty(): self.all_scopes[0]}
         self.class_paths: ClassPaths = {TransformUtil.Path.empty(): []}  # seed root
+        self.block_link_order: List[TransformUtil.Path] = []
 
         self.design = design
 
     def process_blocklike(
         self, path: TransformUtil.Path, block: Union[edgir.Link, edgir.LinkArray, edgir.HierarchyBlock]
     ) -> None:
+        self.block_link_order.append(path)
+
         # TODO may need rethought to support multi-board assemblies
         scope = self.scopes[path]  # including footprint and exports, and everything within a link
         internal_scope = scope  # for internal blocks
@@ -253,7 +256,7 @@ def visit_linkarray(self, context: TransformUtil.TransformContext, link: edgir.L
         self.process_blocklike(context.path, link)
 
     @staticmethod
-    def name_net(net: Iterable[TransformUtil.Path], net_prefix: str) -> str:
+    def name_net(net: Iterable[TransformUtil.Path]) -> TransformUtil.Path:
         """Names a net based on all the paths of ports and links that are part of the net."""
         # higher criteria are preferred, True or larger number is preferred
         CRITERIA: List[Callable[[TransformUtil.Path], Union[bool, int]]] = [
@@ -285,9 +288,11 @@ def pin_name_goodness(pin1: TransformUtil.Path, pin2: TransformUtil.Path) -> int
 
         best_path = sorted(net, key=cmp_to_key(pin_name_goodness))[0]
 
-        return net_prefix + str(best_path)
+        return best_path
 
     def scope_to_netlist(self, scope: BoardScope) -> Netlist:
+        path_ordering = {path: i for i, path in enumerate(self.block_link_order)}
+
         # Convert to the netlist format
         seen: Set[TransformUtil.Path] = set()
         nets: List[List[TransformUtil.Path]] = []  # lists preserve ordering
@@ -313,13 +318,17 @@ def scope_to_netlist(self, scope: BoardScope) -> Netlist:
             if pin_to_net[connected1] is not pin_to_net[connected2]:
                 raise InvalidPackingException(f"packed pins {connected1}, {connected2} not connected")
 
+        named_nets = sorted(
+            [(self.name_net(net), net) for net in nets],
+            key=lambda pair: path_ordering[pair[0].link_component(must_have_link=False)],
+        )
+
         board_refdes_prefix = self.design.get_value(("refdes_prefix",))
         if board_refdes_prefix is not None:
             assert isinstance(board_refdes_prefix, str)
             net_prefix = board_refdes_prefix
         else:
             net_prefix = ""
-        named_nets = {self.name_net(net, net_prefix): net for net in nets}
 
         def port_ignored_paths(path: TransformUtil.Path) -> bool:  # ignore link ports for netlisting
             return bool(path.links) or any(
@@ -329,11 +338,14 @@ def port_ignored_paths(path: TransformUtil.Path) -> bool:  # ignore link ports f
         netlist_footprints = [footprint for path, footprint in scope.footprints.items()]
         netlist_nets = [
             Net(
-                name,
-                list(chain(*[scope.pins[port] for port in net if port in scope.pins])),
+                net_prefix + str(name),
+                sorted(
+                    list(chain(*[scope.pins[port] for port in net if port in scope.pins])),
+                    key=lambda pin: ((path_ordering[pin.block_path]), pin.pin_name),
+                ),
                 [port for port in net if not port_ignored_paths(port)],
             )
-            for name, net in named_nets.items()
+            for name, net in named_nets
         ]
         netlist_nets = [net for net in netlist_nets if net.pins]  # prune empty nets
 

examples/BasicKeyboard/BasicKeyboard.net

@@ -186,21 +186,21 @@
 (net (code 8) (name "mcu.vusb_out")
   (node (ref U1) (pin 14)))
 (net (code 9) (name "sw.d[0,0].cathode")
-  (node (ref D1) (pin 1))
-  (node (ref SW1) (pin 1)))
+  (node (ref SW1) (pin 1))
+  (node (ref D1) (pin 1)))
 (net (code 10) (name "sw.d[0,1].cathode")
-  (node (ref D2) (pin 1))
-  (node (ref SW2) (pin 1)))
+  (node (ref SW2) (pin 1))
+  (node (ref D2) (pin 1)))
 (net (code 11) (name "sw.d[0,2].cathode")
-  (node (ref D3) (pin 1))
-  (node (ref SW3) (pin 1)))
+  (node (ref SW3) (pin 1))
+  (node (ref D3) (pin 1)))
 (net (code 12) (name "sw.d[1,0].cathode")
-  (node (ref D4) (pin 1))
-  (node (ref SW4) (pin 1)))
+  (node (ref SW4) (pin 1))
+  (node (ref D4) (pin 1)))
 (net (code 13) (name "sw.d[1,1].cathode")
-  (node (ref D5) (pin 1))
-  (node (ref SW5) (pin 1)))
+  (node (ref SW5) (pin 1))
+  (node (ref D5) (pin 1)))
 (net (code 14) (name "sw.d[1,2].cathode")
-  (node (ref D6) (pin 1))
-  (node (ref SW6) (pin 1))))
+  (node (ref SW6) (pin 1))
+  (node (ref D6) (pin 1))))
 )

examples/BasicKeyboard/BasicKeyboard.svgpcb.js

@@ -16,12 +16,12 @@ board.setNetlist([
   {name: "mcu.pwr_out", pads: [["U1", "12"]]},
   {name: "mcu.gnd", pads: [["U1", "13"]]},
   {name: "mcu.vusb_out", pads: [["U1", "14"]]},
-  {name: "sw.d[0,0].cathode", pads: [["D1", "1"], ["SW1", "1"]]},
-  {name: "sw.d[0,1].cathode", pads: [["D2", "1"], ["SW2", "1"]]},
-  {name: "sw.d[0,2].cathode", pads: [["D3", "1"], ["SW3", "1"]]},
-  {name: "sw.d[1,0].cathode", pads: [["D4", "1"], ["SW4", "1"]]},
-  {name: "sw.d[1,1].cathode", pads: [["D5", "1"], ["SW5", "1"]]},
-  {name: "sw.d[1,2].cathode", pads: [["D6", "1"], ["SW6", "1"]]}
+  {name: "sw.d[0,0].cathode", pads: [["SW1", "1"], ["D1", "1"]]},
+  {name: "sw.d[0,1].cathode", pads: [["SW2", "1"], ["D2", "1"]]},
+  {name: "sw.d[0,2].cathode", pads: [["SW3", "1"], ["D3", "1"]]},
+  {name: "sw.d[1,0].cathode", pads: [["SW4", "1"], ["D4", "1"]]},
+  {name: "sw.d[1,1].cathode", pads: [["SW5", "1"], ["D5", "1"]]},
+  {name: "sw.d[1,2].cathode", pads: [["SW6", "1"], ["D6", "1"]]}
 ])
 
 const limit0 = pt(-0.07874015748031496, -0.07874015748031496);