nvidia: don't report fake PCIe link on unified-memory SoC GPUs - #1
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On unified-memory SoC platforms such as the DGX Spark (GB10), the GPU is attached via an on-die interconnect (NVLink-C2C) rather than a PCIe link. NVML nevertheless returns NVML_SUCCESS for the current PCIe link generation/width, but with placeholder values (GEN 1 @ 1x), which nvtop surfaces as if they were real. Since unified-memory devices have no PCIe framebuffer link, only report PCIe link generation/width on discrete (non-unified) GPUs so the header falls back to N/A instead of showing a misleading link. Pcie RX/TX throughput already shows N/A on these devices because NVML returns NVML_ERROR_NOT_SUPPORTED there. Closes the PCIe misreporting part of Syllo#426.
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Superseded by upstream PR Syllo#499 |
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Summary
Fixes the PCIe misreporting portion of Syllo#426 on unified-memory SoC GPUs such as the DGX Spark (GB10).
On the GB10, the GPU is attached via NVLink-C2C (on-die interconnect), not a PCIe slot. However, NVML's
nvmlDeviceGetCurrPcieLinkGeneration/nvmlDeviceGetCurrPcieLinkWidthreturnNVML_SUCCESSwith placeholder values (GEN 1 @ 1x), which nvtop displayed as if they were a real PCIe link.These devices are already detected (unified memory →
has_unified_memory), so this PR gates PCIe link gen/width reporting on not being unified memory, making the header fall back toN/A. PCIe RX/TX throughput was alreadyN/Ahere because NVML returnsNVML_ERROR_NOT_SUPPORTED.Before (master)
After
Memory (
MEM[...Gi]) is already reported correctly on GB10 via the Syllo#466 unified-memory fallback; fan and memory-clock remain correctlyN/Asince the SoC does not expose them through NVML.Validation
has_unified_memoryis only set when NVML reports unified/SoC memory.