Submiting HW2

adder.t.v

@@ -6,9 +6,29 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
-
+    //behavioralFullAdder bAdder (sum, carryout, a, b, carryin);
+    structuralFullAdder sAdder (sum, carryout, a, b, carryin);
     initial begin
-        // Your test code here
+
+    $dumpfile("adder.vcd");
+	$dumpvars;
+
+    $display("A B Cin |S Cout|Expected Output");
+    a=0;b=0;carryin=0; #1000
+    $display("%b  %b  %b | %b  %b | 0  0", a, b, carryin, sum, carryout);
+    a=0;b=0;carryin=1; #1000
+    $display("%b  %b  %b | %b  %b | 1  0", a, b, carryin, sum, carryout);
+    a=0;b=1;carryin=0; #1000
+    $display("%b  %b  %b | %b  %b | 1  0", a, b, carryin, sum, carryout);  
+    a=0;b=1;carryin=1; #1000
+    $display("%b  %b  %b | %b  %b | 0  1", a, b, carryin, sum, carryout); 
+    a=1;b=0;carryin=0; #1000
+    $display("%b  %b  %b | %b  %b | 1  0", a, b, carryin, sum, carryout); 
+    a=1;b=0;carryin=1; #1000
+    $display("%b  %b  %b | %b  %b | 0  1", a, b, carryin, sum, carryout); 
+    a=1;b=1;carryin=0; #1000
+    $display("%b  %b  %b | %b  %b | 0  1", a, b, carryin, sum, carryout); 
+    a=1;b=1;carryin=1; #1000
+    $display("%b  %b  %b | %b  %b | 1  1", a, b, carryin, sum, carryout);  
     end
 endmodule

adder.v

@@ -1,4 +1,7 @@
 // Adder circuit
+`define AND and #50
+`define OR or #50
+`define XOR xor #50
 
 module behavioralFullAdder
 (
@@ -20,5 +23,10 @@ module structuralFullAdder
     input b, 
     input carryin
 );
-    // Your adder code here
+    wire XORout, ANDout1, ANDout2;
+    `XOR XOR1(XORout, a, b);
+    `XOR XOR2(sum, XORout, carryin);
+    `AND AND1(ANDout1, XORout, carryin);
+    `AND AND2(ANDout2, a, b);
+    `OR ORgate(carryout, ANDout1, ANDout2);
 endmodule

decoder.t.v

@@ -7,10 +7,12 @@ module testDecoder ();
     reg enable;
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    //behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
 
     initial begin
+    $dumpfile("decoder.vcd");
+    $dumpvars;
     $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
     enable=0;addr0=0;addr1=0; #1000 
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);

decoder.v

@@ -1,4 +1,7 @@
 // Decoder circuit
+`define AND and #50
+`define OR or #50
+`define NOT not #50
 
 module behavioralDecoder
 (
@@ -17,6 +20,12 @@ module structuralDecoder
     input address0, address1,
     input enable
 );
-    // Your decoder code here
+	wire nA0, nA1;
+	`NOT A0inv(nA0, address0); 
+	`NOT A1inv(nA1, address1);
+	`AND AG0(out0, enable, nA0, nA1);
+	`AND AG1(out1, enable, address0, nA1);
+	`AND AG2(out2, enable, nA0, address1);
+	`AND AG3(out3, enable, address0, address1);
 endmodule
 

multiplexer.t.v

@@ -3,5 +3,42 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
-  // Your test code here
+    reg addr0, addr1;
+    reg in0, in1, in2, in3;
+    wire out0;
+
+    //behavioralMultiplexer bmux(out, addr0, addr1, in0, in1, in2, in3);
+    structuralMultiplexer smux(out, addr0, addr1, in0, in1, in2, in3);
+
+    initial begin
+    $dumpfile("multiplexer.vcd");
+	$dumpvars;
+    $display("A0 A1 O0 O1 O2 O3 | out | Expected Output");
+    //Change in0
+    addr0=0;addr1=0;in0=0;in1=0;in2=0;in3=0; #1000 
+    $display("%b  %b  %b  %b  %b  %b | %b | in0:0", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=0;addr1=0;in0=1; #1000    
+    $display("%b  %b  %b  %b  %b  %b | %b | in0:1", addr0, addr1, in0, in1, in2, in3, out);
+    //Change in1
+    addr0=1;addr1=0;in0=0; #1000 
+    $display("%b  %b  %b  %b  %b  %b | %b | in1:0", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=1;addr1=0;in1=1; #1000 
+    $display("%b  %b  %b  %b  %b  %b | %b | in1:1", addr0, addr1, in0, in1, in2, in3, out);
+    //Change in2
+    addr0=0;addr1=1;in1=0; #1000 
+    $display("%b  %b  %b  %b  %b  %b | %b | in2:0", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=0;addr1=1;in2=1; #1000 
+    $display("%b  %b  %b  %b  %b  %b | %b | in2:1", addr0, addr1, in0, in1, in2, in3, out);
+    //Change in3
+    addr0=1;addr1=1;in2=0; #1000 
+    $display("%b  %b  %b  %b  %b  %b | %b | in3:0", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=1;addr1=1;in3=1; #1000 
+    $display("%b  %b  %b  %b  %b  %b | %b | in3:1", addr0, addr1, in0, in1, in2, in3, out);
+    //Other cases
+    addr0=0;addr1=0;in0=1;in1=1;in2=1;in3=1; #1000 
+    $display("%b  %b  %b  %b  %b  %b | %b | in0:1", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=0;addr1=0;in0=0;in1=1;in2=1;in3=1; #1000 
+    $display("%b  %b  %b  %b  %b  %b | %b | in0:0", addr0, addr1, in0, in1, in2, in3, out);
+    $display("Assume the other inputs work like in0, etc.. Because the logic is symmetric.");
+    end
 endmodule

multiplexer.v

@@ -1,4 +1,7 @@
 // Multiplexer circuit
+`define NAND nand #50
+`define OR or #50
+`define NOT not #50
 
 module behavioralMultiplexer
 (
@@ -19,6 +22,15 @@ module structuralMultiplexer
     input address0, address1,
     input in0, in1, in2, in3
 );
-    // Your multiplexer code here
+    wire nA0, nA1;
+    wire out0, out1, out2, out3;
+    `NOT A0inv(nA0, address0); 
+    `NOT A1inv(nA1, address1);
+    `NAND AG0(out0, nA0, nA1, in0);
+    `NAND AG1(out1, address0, nA1, in1);
+    `NAND AG2(out2, address1, nA0, in2);
+    `NAND AG3(out3, address0, address1, in3);
+    `NAND AGT(out, out0, out1, out2, out3);
+
 endmodule