Serena HW2

.gitignore

@@ -0,0 +1,3 @@
+
+*.o
+*.vcd

adder.t.v

@@ -6,9 +6,28 @@ module testFullAdder();
     reg a, b, carryin;
     wire sum, carryout;
 
-    behavioralFullAdder adder (sum, carryout, a, b, carryin);
+    structuralFullAdder adder (sum, carryout, a, b, carryin);
 
     initial begin
-        // Your test code here
+        $dumpfile("adder.vcd");
+        $dumpvars(0, testFullAdder);
+
+        $display("IA IB Ci | Su Co | Expected Output");
+        a=0; b=0; carryin=0; #1000 
+        $display("%b  %b  %b  |  %b  %b |  0  0", a, b, carryin, sum, carryout);
+        a=1; b=0; carryin=0; #1000 
+        $display("%b  %b  %b  |  %b  %b |  1  0", a, b, carryin, sum, carryout);
+        a=0; b=1; carryin=0; #1000 
+        $display("%b  %b  %b  |  %b  %b |  1  0", a, b, carryin, sum, carryout);
+        a=0; b=0; carryin=1; #1000 
+        $display("%b  %b  %b  |  %b  %b |  1  0", a, b, carryin, sum, carryout);
+        a=1; b=1; carryin=0; #1000 
+        $display("%b  %b  %b  |  %b  %b |  0  1", a, b, carryin, sum, carryout);
+        a=0; b=1; carryin=1; #1000 
+        $display("%b  %b  %b  |  %b  %b |  0  1", a, b, carryin, sum, carryout);
+        a=1; b=0; carryin=1; #1000 
+        $display("%b  %b  %b  |  %b  %b |  0  1", a, b, carryin, sum, carryout);
+        a=1; b=1; carryin=1; #1000 
+        $display("%b  %b  %b  |  %b  %b |  1  1", a, b, carryin, sum, carryout);
     end
 endmodule

adder.v

@@ -1,5 +1,12 @@
 // Adder circuit
 
+// define gates with delays
+`define AND and #50
+`define NAND nand #50
+`define OR or #50
+`define NOT not #50
+`define XOR xor #50
+
 module behavioralFullAdder
 (
     output sum, 
@@ -20,5 +27,36 @@ module structuralFullAdder
     input b, 
     input carryin
 );
-    // Your adder code here
+    wire AB, BC, AC;
+    wire ABorBC;
+
+    // put a one in carryout if at least 2 inputs are 1
+    `AND ABgate (AB, a, b);
+    `AND BCgate (BC, b, carryin);
+    `AND ACgate (AC, a, carryin);
+    `OR ABorBCgate (ABorBC, AB, BC);
+    `OR COUTgate (carryout, ABorBC, AC);
+
+    wire AorB, BorC, AorC, AorBBorC, AorBBorCAorC;
+    wire nABC, twoTrue;
+    wire nAorB, nBorC, nAorBorC;
+    wire nsum;
+    // test where two inputs are 1
+    `OR AorBgate (AorB, a, b);
+    `OR BorCgate (BorC, b, carryin);
+    `OR AorCgate (AorC, a, carryin);
+    `AND AorBBorCgate (AorBBorC, AorB, BorC);
+    `AND AorBBorCAorCgate (AorBBorCAorC, AorBBorC, AorC);
+    `NAND nABCgate (nABC, AB, BC);
+    `AND twoTruegate (twoTrue, nABC, AorBBorCAorC);
+
+    // test where no inputs are 1
+    `NOT nAorBgate (nAorB, AorB);
+    `NOT nBorCgate (nBorC, BorC);
+    `AND nAorBorCgate (nAorBorC, nAorB, nBorC);
+
+    // find the ones that should not have 1 in sum
+    `OR notSUMgate (nsum, twoTrue, nAorBorC);
+    `NOT SUMgate (sum, nsum);
+
 endmodule

decoder.t.v

@@ -4,13 +4,16 @@
 
 module testDecoder (); 
     reg addr0, addr1;
-    reg enable;
+    reg enable;     // reg - inputs, instantiate as a variable 
+                    //that remembers the last thing assigned
     wire out0,out1,out2,out3;
 
-    behavioralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable);
-    //structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
+    structuralDecoder decoder (out0,out1,out2,out3,addr0,addr1,enable); // Swap after testing
 
     initial begin
+    $dumpfile("decoder.vcd");
+    $dumpvars(0, testDecoder);
+
     $display("En A0 A1| O0 O1 O2 O3 | Expected Output");
     enable=0;addr0=0;addr1=0; #1000 
     $display("%b  %b  %b |  %b  %b  %b  %b | All false", enable, addr0, addr1, out0, out1, out2, out3);

decoder.v

@@ -1,5 +1,10 @@
 // Decoder circuit
 
+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+
 module behavioralDecoder
 (
     output out0, out1, out2, out3,
@@ -17,6 +22,21 @@ module structuralDecoder
     input address0, address1,
     input enable
 );
-    // Your decoder code here
+    wire n0, n1;
+    wire use0, use1, use2, use3;
+
+    `NOT n0gate (n0, address0);
+    `NOT n1gate (n1, address1);
+
+    `AND use0gate (use0, n0, n1);
+    `AND use1gate (use1, address0, n1);
+    `AND use2gate (use2, n0, address1);
+    `AND use3gate (use3, address0, address1);
+
+    `AND out0gate (out0, enable, use0);
+    `AND out1gate (out1, enable, use1);
+    `AND out2gate (out2, enable, use2);
+    `AND out3gate (out3, enable, use3);
+
 endmodule
 

multiplexer.t.v

@@ -3,5 +3,33 @@
 `include "multiplexer.v"
 
 module testMultiplexer ();
-  // Your test code here
+    reg addr0, addr1;
+    reg in0, in1, in2, in3;
+
+    wire out;
+
+    structuralMultiplexer mux (out, addr0, addr1, in0, in1, in2, in3);
+
+    initial begin
+    $dumpfile("multiplexer.vcd");
+    $dumpvars(0, testMultiplexer);
+
+    $display("A0 A1 | I0 I1 I2 I3 | Ou | Expected Output");
+    addr0=0; addr1=0; in0=0; in1=0; in2=0; in3=0; #1000 
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | false", addr0, addr1, in0, in1, in2, in3, out);
+    in0=1; #1000 
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | true", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=1; addr1=0; #1000 
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | false", addr0, addr1, in0, in1, in2, in3, out);
+    in1=1; #1000 
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | true", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=0; addr1=1; #1000 
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | false", addr0, addr1, in0, in1, in2, in3, out);
+    in2=1; #1000 
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | true", addr0, addr1, in0, in1, in2, in3, out);
+    addr0=1; addr1=1; #1000 
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | false", addr0, addr1, in0, in1, in2, in3, out);
+    in3=1; #1000 
+    $display("%b  %b  |  %b  %b  %b  %b  |  %b | true", addr0, addr1, in0, in1, in2, in3, out);
+    end
 endmodule

multiplexer.v

@@ -1,5 +1,10 @@
 // Multiplexer circuit
 
+// define gates with delays
+`define AND and #50
+`define OR or #50
+`define NOT not #50
+
 module behavioralMultiplexer
 (
     output out,
@@ -19,6 +24,27 @@ module structuralMultiplexer
     input address0, address1,
     input in0, in1, in2, in3
 );
-    // Your multiplexer code here
+    wire n0, n1;
+    wire sel0, sel1, sel2, sel3;
+    wire out0, out1, out2, out3;
+    wire out01, out23;
+
+    `NOT n0gate (n0, address0);
+    `NOT n1gate (n1, address1);
+
+    `AND sel0gate (sel0, n0, n1);
+    `AND sel1gate (sel1, address0, n1);
+    `AND sel2gate (sel2, n0, address1);
+    `AND sel3gate (sel3, address0, address1);
+
+    `AND out0gate (out0, sel0, in0);
+    `AND out1gate (out1, sel1, in1);
+    `AND out2gate (out2, sel2, in2);
+    `AND out3gate (out3, sel3, in3);
+
+    `OR out01gate (out01, out0, out1);
+    `OR out23gate (out23, out2, out3);
+    `OR outgate (out, out01, out23);
+
 endmodule