[Review Only] Remove all PIN related code and reimplement them with RISC-V ISA#1
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gtxzsxxk wants to merge 51 commits into
Open
[Review Only] Remove all PIN related code and reimplement them with RISC-V ISA#1gtxzsxxk wants to merge 51 commits into
gtxzsxxk wants to merge 51 commits into
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…instructions support
… the sim threading
…n if they are not ldst
… join when new trace come
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PIN is very old and not compiler-friendly enough for today's toolchains. So I remove all PIN related code and reimplement them with the novel ISA RISC-V because it is more simple compared to x86's multiple instructions.
Now this version support reading trace exported from qemu_tracer and integrate the tracing mechanism with zsim's inner simulation.
This PR is only for the code review and do not merge