Prepare for next version with more features, better docs, and some fixes

.scalafmt.conf

@@ -1,4 +1,4 @@
-version = 3.10.5
+version = 3.10.7
 runner.dialect = scala3
 
 maxColumn = 100

CLAUDE.md

@@ -0,0 +1,116 @@
+# DFHDL — Claude Code Guide
+
+> **For contributors and Claude Code users working on the DFHDL project.**
+> This file is version-controlled — keep it updated as the project structure evolves.
+> Skills for deeper topics live in [.claude/commands/](.claude/commands/).
+
+## Project Overview
+
+**DFHDL (DFiant HDL)** is a dataflow hardware description language embedded as a Scala 3 library. It provides timing-agnostic and device-agnostic hardware design with three levels of abstraction:
+
+- **Dataflow (DF)**: Timing-agnostic, uses dataflow firing rules
+- **Register-Transfer (RT)**: Equivalent to Chisel/Amaranth
+- **Event-Driven (ED)**: Equivalent to Verilog/VHDL
+
+Outputs: Verilog, SystemVerilog, VHDL.
+
+## Build System
+
+**Tool**: SBT 1.12.2 — **Scala**: 3.8.1 (nightly resolver enabled)
+
+```bash
+sbt compile          # compile all subprojects
+sbt test             # run all unit tests
+sbt testApps         # run simulation/app tests (requires OSS CAD tools)
+sbt quickTestSetup   # limit test scope to lib/Playground.scala only (fast iteration)
+sbt clearSandbox     # delete sandbox/ directory
+sbt docExamplesRefUpdate  # copy generated HDL from sandbox/ to lib/src/test/resources/ref/
+```
+
+## Subproject Structure
+
+Dependencies flow left to right:
+
+```
+internals → plugin → compiler_ir → core → compiler_stages → lib → platforms
+                                                                 → ips
+```
+
+| Subproject | SBT name | Directory | Purpose |
+|---|---|---|---|
+| internals | `internals` | `internals/` | Core utilities: BitVector, MetaContext, DiskCache, etc. |
+| plugin | `plugin` | `plugin/` | Scala 3 compiler plugin (9 phases) |
+| compiler_ir | `compiler_ir` | `compiler/ir/` | IR/AST data structures, type system |
+| core | `core` | `core/` | HDL language abstractions (DFVal, DFType, Design) |
+| compiler_stages | `compiler_stages` | `compiler/stages/` | 50+ transformation stages for code generation |
+| lib | `lib` | `lib/` | Standard library: arithmetic, memory, ALU, crypto |
+| platforms | `platforms` | `platforms/` | FPGA board wrappers (Apache 2.0 licensed) |
+| ips | `ips` | `ips/` | IP cores library |
+
+## Compiler Plugin Phases
+
+Located in `plugin/src/main/scala/plugin/`:
+
+1. `PreTyperPhase` — pre-typing transformations
+2. `TopAnnotPhase` — top-level annotation processing
+3. `MetaContextPlacerPhase` — places meta-context markers
+4. `LoopFSMPhase` — loop-to-FSM transformations
+5. `CustomControlPhase` — custom control flow
+6. `DesignDefsPhase` — design definition processing
+7. `MetaContextDelegatePhase` — meta-context delegation
+8. `MetaContextGenPhase` — meta-context code generation
+9. `OnCreateEventsPhase` — on-create event handling
+
+The plugin is applied to `core`, `compiler_stages`, `lib`, `platforms`, and `ips` via `pluginUseSettings` / `pluginTestUseSettings`.
+
+## Testing
+
+**Framework**: munit 1.2.2
+
+- **Stage tests**: `compiler/stages/src/test/scala/StagesSpec/` — tests each compiler stage
+- **Doc example tests**: `lib/src/test/scala/docExamples/` — validates documentation examples
+- **Arithmetic tests**: `lib/src/test/scala/ArithSpec/`
+- **AES tests**: `lib/src/test/scala/AES/`
+- **Base class**: `DesignSpec` — provides `assertCodeString()` and `assertElaborationErrors()`
+- **Playground**: `lib/src/test/scala/Playground.scala` — used for quick local iteration via `quickTestSetup`
+
+Generated HDL reference files live in `lib/src/test/resources/ref/`. Update them with `sbt docExamplesRefUpdate` after intentional output changes.
+
+`testApps` auto-detects installed simulation tools (ghdl, nvc, verilator, iverilog, questa, vivado) and runs the AES cipher simulation against all available tool/dialect combinations.
+
+## Code Conventions
+
+- **Formatting**: scalafmt 3.10.6, max 100 columns, Scala 3 dialect
+  - Optional braces removed (`removeOptionalBraces = oldSyntaxToo`)
+  - End markers inserted for blocks ≥ 15 lines
+  - Run `scalafmt` before committing
+- **Compiler flags**: `-language:strictEquality`, `-unchecked`, `-feature`, `-preview`, `-deprecation`
+- **Implicit conversions**: only enabled in `internals` and `compiler_ir` via `implicitConversionSettings`
+- **Naming**: `DF`-prefixed types (e.g., `DFVal`, `DFType`), `DFC` for context; stage names follow `Drop*`, `Add*`, `Connect*`, `Break*` patterns
+- **Package root**: `dfhdl.*`
+
+## Key Files
+
+| File | Purpose |
+|---|---|
+| `build.sbt` | Multi-project build definition |
+| `project/DFHDLCommands.scala` | Custom SBT commands |
+| `.scalafmt.conf` | Code formatting rules |
+| `mkdocs.yml` | Documentation site config |
+| `sandbox/` | Generated output during tests/apps (gitignored, cleared by `clearSandbox`) |
+| `lib/src/test/resources/ref/` | Reference HDL output snapshots for regression tests |
+
+## External Simulation Tools (for `testApps`)
+
+CI installs these via OSS CAD Suite:
+- **Verilog**: verilator, iverilog (sv2005 skipped for iverilog), questa, vivado
+- **VHDL**: ghdl, nvc, questa, vivado (v2008 skipped for vivado)
+
+## Claude Instructions
+
+- When asked to **create a new compiler stage** or **modify an existing compiler stage**, always invoke the `/new-stage` skill before doing any work.
+
+## Licenses
+
+- Main library (`internals`, `plugin`, `compiler_ir`, `core`, `compiler_stages`, `lib`, `ips`): **LGPL v3.0**
+- `platforms/`: **Apache 2.0**

build.sbt

@@ -144,11 +144,11 @@ lazy val platforms = project
 lazy val dependencies =
   new {
     private val scodecV = "1.2.4"
-    private val munitV = "1.2.2"
-    private val airframelogV = "2025.1.27"
-    private val oslibV = "0.11.7"
-    private val scallopV = "5.3.0"
-    private val upickleV = "4.4.2"
+    private val munitV = "1.2.4"
+    private val airframelogV = "2026.1.4"
+    private val oslibV = "0.11.8"
+    private val scallopV = "6.0.0"
+    private val upickleV = "4.4.3"
 
     val scodec = "org.scodec" %% "scodec-bits" % scodecV
     val munit = "org.scalameta" %% "munit" % munitV % Test

compiler/ir/src/main/scala/dfhdl/compiler/analysis/DFValAnalysis.scala

@@ -65,7 +65,7 @@ object StrippedPortByNameSelect:
 object DefaultOfDesignParam:
   def unapply(dfVal: DFVal)(using MemberGetSet): Option[DFVal.DesignParam] =
     dfVal.originMembers.collectFirst {
-      case dp: DFVal.DesignParam if dp.defaultRef.get == dfVal => dp
+      case dp: DFVal.DesignParam if dp.defaultValRef.get == dfVal => dp
     }
 
 object OpaqueActual:
@@ -84,8 +84,7 @@ object AsOpaque:
 
 object Bind:
   def unapply(alias: DFVal.Alias)(using MemberGetSet): Option[DFVal] =
-    if (alias.getTagOf[BindTag].isDefined)
-      Some(alias.relValRef.get)
+    if (alias.hasTagOf[BindTag]) Some(alias.relValRef.get)
     else None
 
 object ClkEdge:
@@ -200,6 +199,8 @@ extension (member: DFMember)
   def originMembersNoTypeRef(using MemberGetSet): Set[DFMember] =
     getSet.designDB.originMemberTableNoTypeRef.getOrElse(member, Set())
 
+type DFValReadDep = TextOut | DFNet | DFVal | DFConditional.Block
+
 extension (dfVal: DFVal)
   def getPartialAliases(using MemberGetSet): Set[DFVal.Alias.Partial] =
     dfVal.originMembers.flatMap {
@@ -234,8 +235,8 @@ extension (dfVal: DFVal)
     dfVal.originMembers.view
       .collect { case dfVal: DFVal => dfVal }
       .exists(dfVal => cond(dfVal) || dfVal.existsInComposedReadDeps(cond))
-  def getReadDeps(using MemberGetSet): Set[TextOut | DFNet | DFVal | DFConditional.Block] =
-    val fromRefs: Set[TextOut | DFNet | DFVal | DFConditional.Block] =
+  def getReadDeps(using MemberGetSet): Set[DFValReadDep] =
+    val fromRefs: Set[DFValReadDep] =
       dfVal.originMembersNoTypeRef.flatMap {
         case net: DFNet =>
           net match
@@ -260,12 +261,13 @@ extension (dfVal: DFVal)
           .toSet ++ fromRefs
       case _ => fromRefs
   end getReadDeps
-  def isReferencedByAnyDcl(using MemberGetSet): Boolean =
+  def isReferencedByAnyDclOrDesign(using MemberGetSet): Boolean =
     dfVal.originMembers.view.exists {
-      case _: DFVal.Dcl => true
-      case DclConst()   => true
-      case dfVal: DFVal => dfVal.isReferencedByAnyDcl
-      case _            => false
+      case _: DFVal.Dcl     => true
+      case DclConst()       => true
+      case _: DFDesignBlock => true
+      case dfVal: DFVal     => dfVal.isReferencedByAnyDclOrDesign
+      case _                => false
     }
 
   @tailrec private def flatName(member: DFVal, suffix: String)(using MemberGetSet): String =
@@ -415,11 +417,12 @@ extension (origVal: DFVal)
       forceIncludeOrigVal: Boolean
   )(using MemberGetSet): List[DFVal] =
     if (origVal.isAnonymous && !origVal.isGlobal || forceIncludeOrigVal)
-      origVal :: origVal.getRefs.map(_.get).view
-        .flatMap {
-          case dfVal: DFVal => dfVal.collectRelMembersRecur(false)
-          case _            => Nil
-        }.toList
+      origVal ::
+        origVal.getRefs.map(_.get).view
+          .flatMap {
+            case dfVal: DFVal => dfVal.collectRelMembersRecur(false)
+            case _            => Nil
+          }.toList
     else Nil
   @targetName("collectRelMembersDFVal")
   def collectRelMembers(includeOrigVal: Boolean)(using MemberGetSet): List[DFVal] =