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Func.prot_=~ compared meta (including auto-generated names), which caused identical parameterized designs with computed sub-params to be classified as different groups. The auto-name on a Func node derives from the parent's instance variable name (e.g. inst_a vs inst_b), making structurally identical designs appear different. Removing the meta comparison from Func.prot_=~ fixes the grouping — a Func's structural identity is fully determined by (dfType, op, args). Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
…or connection in ED domain outside a process.
Explain that plain `val` can be used for intermediate expressions inside process blocks, and warn that `VAR` inside clocked processes becomes register storage. Closes #43 Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
…oops, type selection, bit replication - Add @top annotation section and clog2 type reuse pattern (from-verilog) - Add mixed-width signed arithmetic worked examples (from-verilog) - Add type selection heuristic for UInt vs Bits vs SInt (from-verilog) - Add .repeat bit replication section (from-verilog) - Add generate-for loops and elaboration-time conditional note (from-verilog) - Add cross-reference to naming section for built-in conflicts (from-verilog) - Populate naming guide with reserved names and resolution patterns (naming) - Create loops guide with elaboration-time, ED, and RT loop semantics (loops) - Note Int <> CONST accepts full Scala Int range (type-system) Closes #42 #43 #44 #47 #48 #49 #50 #51 #52 #53 #57 #58 #59 #60 #61 #64 Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Fixes #371 #370 #369 #372