Updates + website vulnerability removal#396

Merged

soronpo merged 13 commits into

mainfrom

May 31, 2026

Commits on May 17, 2026

docs: fix logical/bitwise not operation documentation for verilog
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docs: clarify ED-domain process synthesizability

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claude
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Commits on May 19, 2026

expand verilog Int sematic warnings
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change SInt slice output to UInt. Fixes https://github.com/DFiantHDL/DFHDL/issues/392
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add `msbits` and `lsbits` slicing to `UInt` and `SInt`
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Commits on May 29, 2026

update platforms module
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support partial selection connection
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update connectivity docs
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docs: connection images through hdelk
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docs: improve hdelk generation
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docs: update elk version
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Commits on May 31, 2026

docs: clarify process syntax, name-collision resolution, dynamic index resize

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remove redundant polyfill source of potential cyber attacks
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