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…y is missing support for match expressions (lack of MatchWrapper in Exact.scala) and has a problem with if expressions.
Local VAR/CONST declarations inside a StepBlock (RT FSM state) could not survive into the generated FSM but were left in place. Generalize the owner-scope handling into a tailrec climbToScope helper that escapes nested conditional and step blocks: for non-VHDL the declaration moves to design level (before the process), for VHDL it moves to process-body level (before the outermost step). Behavior for the existing conditional/process cases is unchanged. Add step-block tests for both backends. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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