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release.yml
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images: pin fpga-isv to v0.2.0 build-test-release #15: Commit 80a077b pushed by soronpo
34m 1s v1.1.1
v1.1.1
34m 1s
images: pin fpga-isv to v0.2.0 build-test-release #14: Commit 80a077b pushed by soronpo
13m 52s main
main
13m 52s
images: add fpga-isv to the hmi image (#3) build-test-release #13: Commit 77a5b3f pushed by soronpo
34m 26s v1.1.0
v1.1.0
34m 26s
images: add fpga-isv to the hmi image (#3) build-test-release #12: Commit 77a5b3f pushed by soronpo
34m 42s main
main
34m 42s
images: add hmi image (ffmpeg) (#2) build-test-release #11: Commit 8d0e1ab pushed by soronpo
44m 29s v1.0.0
v1.0.0
44m 29s
images: add hmi image (ffmpeg) (#2) build-test-release #10: Commit 8d0e1ab pushed by soronpo
9m 12s main
main
9m 12s
release: content-addressed images via a per-tag lockfile (#1) build-test-release #9: Commit 77e5ede pushed by soronpo
32m 57s main
main
32m 57s
remove SDL2 from verilator and pin the latest commit build-test-release #8: Commit d9819f0 pushed by soronpo
33m 12s v0.2.0
v0.2.0
33m 12s
remove SDL2 from verilator and pin the latest commit build-test-release #7: Commit d9819f0 pushed by soronpo
17m 9s main
main
17m 9s
build-test-release build-test-release #6: Manually run by soronpo
32m 50s main
main
32m 50s
ci: temporarily decouple publishing from the DFHDL gate build-test-release #5: Commit 17884c4 pushed by soronpo
1m 37s main
main
1m 37s
ci: gate on DFHDL test and fix sbt arg merging build-test-release #4: Commit 3699ca1 pushed by soronpo
7m 29s main
main
7m 29s
ci: set up DFHDL's Scala toolchain (JDK 17 + sbt/bloop) for the gate build-test-release #3: Commit 226a813 pushed by soronpo
27m 57s main
main
27m 57s
ci: install Apptainer from the official PPA (fixes arm64) build-test-release #2: Commit 04274d8 pushed by soronpo
26m 2s main
main
26m 2s
ci: temporarily gate only against the DFHDL dftools branch build-test-release #1: Commit 1bec065 pushed by soronpo
1m 51s main
main
1m 51s