Fix division instructions to comply with RISC-V spec (VMX-CPU-009)

[crivasr]

The overflow condition was not correctly implemented. We assumed that dividing by -1 would be enough to trigger an overflow, but in reality, it only occurs when dividing i32::MIN by -1. This was not caught by the compliance test because the only instance of division by -1 was specifically used to test for overflows.

8000007c <test_7>:
8000007c:       00700193                li      gp,7
80000080:       800005b7                lui     a1,0x80000
80000084:       fff00613                li      a2,-1
80000088:       02c5d733                divu    a4,a1,a2
8000008c:       00000393                li      t2,0
80000090:       04771863                bne     a4,t2,800000e0 <fail>

The division by 0 worked correctly (note that for the divu case it says 2^{L}-1 and not -2^{L-1}), I just changed it a bit to be more explicit (eg, u32::MAX instead of 0xFFFF_FFFF)