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Associate secure context with task handle
The secure side context management code now checks that the secure context being saved or restored belongs to the task being switched-out or switched-in respectively. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
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53 files changed

+1800
-1357
lines changed

‎portable/ARMv8M/non_secure/port.c‎

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -781,7 +781,8 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
781781
uint32_t ulPC;
782782

783783
#if ( configENABLE_TRUSTZONE == 1 )
784-
uint32_t ulR0;
784+
uint32_t ulR0, ulR1;
785+
extern TaskHandle_t pxCurrentTCB;
785786
#if ( configENABLE_MPU == 1 )
786787
uint32_t ulControl, ulIsTaskPrivileged;
787788
#endif /* configENABLE_MPU */
@@ -812,25 +813,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
812813
ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
813814

814815
/* Allocate and load a context for the secure task. */
815-
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
816+
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
816817
}
817818
#else /* if ( configENABLE_MPU == 1 ) */
818819
{
819820
/* Allocate and load a context for the secure task. */
820-
xSecureContext = SecureContext_AllocateContext( ulR0 );
821+
xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
821822
}
822823
#endif /* configENABLE_MPU */
823824

824-
configASSERT( xSecureContext != NULL );
825-
SecureContext_LoadContext( xSecureContext );
825+
configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
826+
SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
826827
break;
827828

828829
case portSVC_FREE_SECURE_CONTEXT:
829-
/* R0 contains the secure context handle to be freed. */
830+
/* R0 contains TCB being freed and R1 contains the secure
831+
* context handle to be freed. */
830832
ulR0 = pulCallerStackAddress[ 0 ];
833+
ulR1 = pulCallerStackAddress[ 1 ];
831834

832835
/* Free the secure context. */
833-
SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
836+
SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
834837
break;
835838
#endif /* configENABLE_TRUSTZONE */
836839

‎portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c‎

Lines changed: 196 additions & 190 deletions
Large diffs are not rendered by default.

‎portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c‎

Lines changed: 163 additions & 156 deletions
Large diffs are not rendered by default.

‎portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s‎

Lines changed: 104 additions & 91 deletions
Large diffs are not rendered by default.

‎portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,12 @@
2525
* https://github.com/FreeRTOS
2626
*
2727
*/
28+
/* Including FreeRTOSConfig.h here will cause build errors if the header file
29+
contains code not understood by the assembler - for example the 'extern' keyword.
30+
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
31+
the code is included in C files but excluded by the preprocessor in assembly
32+
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
33+
#include "FreeRTOSConfig.h"
2834

2935
EXTERN pxCurrentTCB
3036
EXTERN vTaskSwitchContext

‎portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s‎

Lines changed: 86 additions & 79 deletions
Original file line numberDiff line numberDiff line change
@@ -184,62 +184,65 @@ vClearInterruptMask:
184184
/*-----------------------------------------------------------*/
185185

186186
PendSV_Handler:
187-
mrs r1, psp /* Read PSP in r1. */
188-
ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
189-
ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
187+
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
188+
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
189+
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
190+
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
191+
mrs r2, psp /* Read PSP in r2. */
190192

191193
cbz r0, save_ns_context /* No secure context to save. */
192194
push {r0-r2, r14}
193-
bl SecureContext_SaveContext
195+
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
194196
pop {r0-r3} /* LR is now in r3. */
195197
mov lr, r3 /* LR = r3. */
196-
lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
197-
bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
198+
lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
199+
bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
200+
198201
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
199-
ldr r2, [r3] /* Read pxCurrentTCB. */
202+
ldr r1, [r3] /* Read pxCurrentTCB. */
200203
#if ( configENABLE_MPU == 1 )
201-
subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
202-
str r1, [r2] /* Save the new top of stack in TCB. */
203-
mrs r2, psplim /* r2 = PSPLIM. */
204+
subs r2, r2, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
205+
str r2, [r1] /* Save the new top of stack in TCB. */
206+
mrs r1, psplim /* r1 = PSPLIM. */
204207
mrs r3, control /* r3 = CONTROL. */
205208
mov r4, lr /* r4 = LR/EXC_RETURN. */
206-
stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
209+
stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
207210
#else /* configENABLE_MPU */
208-
subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
209-
str r1, [r2] /* Save the new top of stack in TCB. */
210-
mrs r2, psplim /* r2 = PSPLIM. */
211+
subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
212+
str r2, [r1] /* Save the new top of stack in TCB. */
213+
mrs r1, psplim /* r1 = PSPLIM. */
211214
mov r3, lr /* r3 = LR/EXC_RETURN. */
212-
stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
215+
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
213216
#endif /* configENABLE_MPU */
214217
b select_next_task
215218

216219
save_ns_context:
217220
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
218-
ldr r2, [r3] /* Read pxCurrentTCB. */
221+
ldr r1, [r3] /* Read pxCurrentTCB. */
219222
#if ( configENABLE_FPU == 1 )
220223
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
221224
it eq
222-
vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */
225+
vstmdbeq r2!, {s16-s31} /* Store the FPU registers which are not saved automatically. */
223226
#endif /* configENABLE_FPU */
224227
#if ( configENABLE_MPU == 1 )
225-
subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
226-
str r1, [r2] /* Save the new top of stack in TCB. */
227-
adds r1, r1, #16 /* r1 = r1 + 16. */
228-
stm r1, {r4-r11} /* Store the registers that are not saved automatically. */
229-
mrs r2, psplim /* r2 = PSPLIM. */
228+
subs r2, r2, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
229+
str r2, [r1] /* Save the new top of stack in TCB. */
230+
adds r2, r2, #16 /* r2 = r2 + 16. */
231+
stm r2, {r4-r11} /* Store the registers that are not saved automatically. */
232+
mrs r1, psplim /* r1 = PSPLIM. */
230233
mrs r3, control /* r3 = CONTROL. */
231234
mov r4, lr /* r4 = LR/EXC_RETURN. */
232-
subs r1, r1, #16 /* r1 = r1 - 16. */
233-
stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
235+
subs r2, r2, #16 /* r2 = r2 - 16. */
236+
stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
234237
#else /* configENABLE_MPU */
235-
subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
236-
str r1, [r2] /* Save the new top of stack in TCB. */
237-
adds r1, r1, #12 /* r1 = r1 + 12. */
238-
stm r1, {r4-r11} /* Store the registers that are not saved automatically. */
239-
mrs r2, psplim /* r2 = PSPLIM. */
238+
subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
239+
str r2, [r1] /* Save the new top of stack in TCB. */
240+
adds r2, r2, #12 /* r2 = r2 + 12. */
241+
stm r2, {r4-r11} /* Store the registers that are not saved automatically. */
242+
mrs r1, psplim /* r1 = PSPLIM. */
240243
mov r3, lr /* r3 = LR/EXC_RETURN. */
241-
subs r1, r1, #12 /* r1 = r1 - 12. */
242-
stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
244+
subs r2, r2, #12 /* r2 = r2 - 12. */
245+
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
243246
#endif /* configENABLE_MPU */
244247

245248
select_next_task:
@@ -251,77 +254,81 @@ PendSV_Handler:
251254
mov r0, #0 /* r0 = 0. */
252255
msr basepri, r0 /* Enable interrupts. */
253256

254-
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
255-
ldr r3, [r2] /* Read pxCurrentTCB. */
256-
ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
257+
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
258+
ldr r1, [r3] /* Read pxCurrentTCB. */
259+
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
257260

258261
#if ( configENABLE_MPU == 1 )
259262
dmb /* Complete outstanding transfers before disabling MPU. */
260-
ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
261-
ldr r4, [r2] /* Read the value of MPU_CTRL. */
263+
ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
264+
ldr r4, [r3] /* Read the value of MPU_CTRL. */
262265
bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
263-
str r4, [r2] /* Disable MPU. */
266+
str r4, [r3] /* Disable MPU. */
264267

265-
adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
266-
ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */
267-
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
268-
str r4, [r2] /* Program MAIR0. */
269-
ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
268+
adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
269+
ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */
270+
ldr r3, =0xe000edc0 /* r3 = 0xe000edc0 [Location of MAIR0]. */
271+
str r4, [r3] /* Program MAIR0. */
272+
ldr r3, =0xe000ed98 /* r3 = 0xe000ed98 [Location of RNR]. */
270273
movs r4, #4 /* r4 = 4. */
271-
str r4, [r2] /* Program RNR = 4. */
272-
adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
273-
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
274-
ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
275-
stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
276-
277-
ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
278-
ldr r4, [r2] /* Read the value of MPU_CTRL. */
274+
str r4, [r3] /* Program RNR = 4. */
275+
adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
276+
ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
277+
ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
278+
stmia r3!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
279+
280+
ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
281+
ldr r4, [r3] /* Read the value of MPU_CTRL. */
279282
orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
280-
str r4, [r2] /* Enable MPU. */
283+
str r4, [r3] /* Enable MPU. */
281284
dsb /* Force memory writes before continuing. */
282285
#endif /* configENABLE_MPU */
283286

284287
#if ( configENABLE_MPU == 1 )
285-
ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
286-
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
288+
ldmia r2!, {r0, r1, r3, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
289+
msr psplim, r1 /* Restore the PSPLIM register value for the task. */
287290
msr control, r3 /* Restore the CONTROL register value for the task. */
288291
mov lr, r4 /* LR = r4. */
289-
ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
290-
str r0, [r2] /* Restore the task's xSecureContext. */
292+
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
293+
str r0, [r3] /* Restore the task's xSecureContext. */
291294
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
292-
push {r1,r4}
293-
bl SecureContext_LoadContext /* Restore the secure context. */
294-
pop {r1,r4}
295+
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
296+
ldr r1, [r3] /* Read pxCurrentTCB. */
297+
push {r2, r4}
298+
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
299+
pop {r2, r4}
295300
mov lr, r4 /* LR = r4. */
296-
lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
297-
bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
298-
msr psp, r1 /* Remember the new top of stack for the task. */
301+
lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
302+
bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
303+
msr psp, r2 /* Remember the new top of stack for the task. */
299304
bx lr
300305
#else /* configENABLE_MPU */
301-
ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
302-
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
303-
mov lr, r3 /* LR = r3. */
304-
ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
305-
str r0, [r2] /* Restore the task's xSecureContext. */
306+
ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
307+
msr psplim, r1 /* Restore the PSPLIM register value for the task. */
308+
mov lr, r4 /* LR = r4. */
309+
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
310+
str r0, [r3] /* Restore the task's xSecureContext. */
306311
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
307-
push {r1,r3}
308-
bl SecureContext_LoadContext /* Restore the secure context. */
309-
pop {r1,r3}
310-
mov lr, r3 /* LR = r3. */
311-
lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
312-
bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
313-
msr psp, r1 /* Remember the new top of stack for the task. */
312+
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
313+
ldr r1, [r3] /* Read pxCurrentTCB. */
314+
push {r2, r4}
315+
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
316+
pop {r2, r4}
317+
mov lr, r4 /* LR = r4. */
318+
lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
319+
bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
320+
msr psp, r2 /* Remember the new top of stack for the task. */
314321
bx lr
315322
#endif /* configENABLE_MPU */
316323

317324
restore_ns_context:
318-
ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */
325+
ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */
319326
#if ( configENABLE_FPU == 1 )
320327
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
321328
it eq
322-
vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */
329+
vldmiaeq r2!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */
323330
#endif /* configENABLE_FPU */
324-
msr psp, r1 /* Remember the new top of stack for the task. */
331+
msr psp, r2 /* Remember the new top of stack for the task. */
325332
bx lr
326333
/*-----------------------------------------------------------*/
327334

@@ -335,9 +342,9 @@ SVC_Handler:
335342

336343
vPortFreeSecureContext:
337344
/* r0 = uint32_t *pulTCB. */
338-
ldr r1, [r0] /* The first item in the TCB is the top of the stack. */
339-
ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */
340-
cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */
345+
ldr r2, [r0] /* The first item in the TCB is the top of the stack. */
346+
ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */
347+
cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */
341348
it ne
342349
svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
343350
bx lr /* Return. */

‎portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,9 @@
3636
#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
3737
#endif
3838

39+
void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
40+
void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
41+
3942
void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
4043
{
4144
/* pxSecureContext value is in r0. */

‎portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c‎

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/* Secure port macros. */
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#include "secure_port_macros.h"
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void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
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void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
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void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
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{
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/* pxSecureContext value is in r0. */

‎portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s‎

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SECTION .text:CODE:NOROOT(2)
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THUMB
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/* Including FreeRTOSConfig.h here will cause build errors if the header file
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contains code not understood by the assembler - for example the 'extern' keyword.
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To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
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the code is included in C files but excluded by the preprocessor in assembly
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files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
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#include "FreeRTOSConfig.h"
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PUBLIC SecureContext_LoadContextAsm
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PUBLIC SecureContext_SaveContextAsm
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‎portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s‎

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SECTION .text:CODE:NOROOT(2)
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THUMB
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/* Including FreeRTOSConfig.h here will cause build errors if the header file
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contains code not understood by the assembler - for example the 'extern' keyword.
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To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
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the code is included in C files but excluded by the preprocessor in assembly
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files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
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#include "FreeRTOSConfig.h"
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PUBLIC SecureContext_LoadContextAsm
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PUBLIC SecureContext_SaveContextAsm
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/*-----------------------------------------------------------*/

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