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FreeRTOS / FreeRTOS-Kernel Public

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RISCV Add FPU context save#1250

Merged

xuelix merged 9 commits intoFreeRTOS:mainFreeRTOS/FreeRTOS-Kernel:mainfrom

sifive:s5/jcu/add_fpu_supportsifive/FreeRTOS-Kernel:s5/jcu/add_fpu_supportCopy head branch name to clipboard

Mar 6, 2025

Conversation Commits9 (9)Checks Files changed

Merged

RISCV Add FPU context save#1250
xuelix merged 9 commits intoFreeRTOS:mainfrom
sifive:s5/jcu/add_fpu_support

Commits

Commits on Mar 6, 2025

port: riscv: Fix typo
cubidesj
committed
port: riscv: Split the number of registers and the size of the context
cubidesj
committed
port: riscv: Create some macros for the FPU context
cubidesj
committed
port: riscv: Add a couple of macros that store fpu context
cubidesj
committed
port: riscv: Update the stack init function to include the fpu context size
cubidesj
committed
port: riscv: Add a chip_specific_extensions file that includes the F extension
cubidesj
committed
Update dictionary to include some risc-v instructions
cubidesj
committed
port: riscv: Fix a few typos
cubidesj
committed
port: riscv: Apply @aggarg's sugestions
cubidesj
committed

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