Add support for CPU selection; Update Py2HWSW version.#4
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jjts merged 9 commits intoIObundle:mainfrom Nov 10, 2025
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Add 'CPU' Makefile variable and corresponding 'cpu' python parameter in soc_linux.py; Refactor soc_linux.py
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VexiiRiscv CPU is not yet fully working with linux, but remaining changes of this PR still apply. |
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Pull Request Overview
This PR restructures the soc_linux core configuration to expose CPU selection as a parameter and updates testing to validate multiple CPU options. The changes simplify the parent core parameter passing mechanism and update the py2hwsw dependency.
- Refactored
soc_linux.pyto move attributes outside the parent dictionary and enable CPU selection - Added CPU parameter support to the Makefile build system
- Updated CI workflow to run comprehensive sim-test instead of single sim-run
Reviewed Changes
Copilot reviewed 4 out of 4 changed files in this pull request and generated 2 comments.
| File | Description |
|---|---|
| soc_linux.py | Restructured core attributes dictionary, moved board list and ports to top level, exposed CPU parameter with default "iob_vexriscv" |
| Makefile | Added CPU parameter handling and updated sim-test to validate both iob_vexriscv and iob_naxriscv CPUs |
| default.nix | Updated py2hwsw dependency commit hash and SHA256 |
| .github/workflows/ci.yml | Changed test command from sim-run to sim-test for broader validation coverage |
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Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
P-Miranda
approved these changes
Nov 3, 2025
P-Miranda
approved these changes
Nov 10, 2025
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Add 'CPU' Makefile variable and corresponding 'cpu' python parameter in soc_linux.py; Refactor soc_linux.py.