GitHub - MalakM15/Pipeline-32-bit-RISC-Processor: A 5-stage, 32-bit pipelined RISC processor in Verilog, featuring a single-format ISA (arithmetic, logical, memory, and control-flow ops) and verified via simulation.

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A 5-stage, 32-bit pipelined RISC processor in Verilog, featuring a single-format ISA (arithmetic, logical, memory, and control-flow ops) and verified via simulation.

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Name		Name	Last commit message	Last commit date
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PipelineCode		PipelineCode
Arch_Report_1220184_1220871_1220031.pdf		Arch_Report_1220184_1220871_1220031.pdf

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A 5-stage, 32-bit pipelined RISC processor in Verilog, featuring a single-format ISA (arithmetic, logical, memory, and control-flow ops) and verified via simulation.