MIP Series Firmware Example for Dual Core
The 32001506 family features a dual core microcontroller in which one is dedicated to the radio stack (ARM Cortex M0+) and the ARM Cortex M4 is free for the customer application firmware. It is based on STM32WL55JC microcontroller.
The arm®Cortex®-M0+ is reserved for sub-GHz radio management and implements the radio stack required by the specific version of the 32001506. It uses the LPTIM (LPTIM1/LPTIM2) for stack timing requirements and 32 kB SRAM2 block as volatile working memory.
The arm®Cortex®-M4 is fully available for user application together with all the peripherals not used by the radio part (all except sub-GHz radio components and LPTIM1/LPTIM2). It uses 32 kB SRAM1 block as volatile working memory and shares flash memory with the arm®Cortex®-M0+ core.
IPCC is used to perform bidirectional communication between cores. It is an ST Microcontroller proprietary inter-core communication controller. For details please refer to “RM0453 Reference manual - STM32WL5x advanced arm®-based 32-bit MCUs with sub-GHz radio solution”.
IPCC communication operates on a common RAM memory area shared between arm®Cortex®-M4 and arm®Cortex®-M0+. In 32001506 a 1 kB area is reserved starting from address 0x20008000 to address 0x200083FF. The IPCC shared memory is totally inside SRAM2 block, so it does not affect arm®Cortex®-M4 available RAM.
For more information, please refer to the documents downloadable from the official MIPOT website. Registration is required.
Designed to test the capabilities of the dual core module, this firmware forwards messages received on the serial line (UART/LPUART) to the M0+ core via IPCC and vice versa. As an initial step, the microcontroller dynamically selects the active serial communication line upon receiving the first signal. This design choice is specific to this example firmware, which primarily serves to illustrate the 32001506 module's functionalities, including IPCC communication and command execution.
Build with MIPOT 30001506CEU DevKit.
- 30001506AEU - 868 MHz Wireless M-Bus
- 30001506BEU - 868 MHz LoRaWAN
- 30001506CEU - 868 MHz LoRa Mipot
- 30001506DEU - 868 MHz LoRa Modem
- 30001506FEU - 868 MHz Dual Stack (LoRaWAN + LoRa Modem)
- 30001506BUS - 915 MHz LoRaWAN
- Application
| PAD | Description | PAD | Description | |
|---|---|---|---|---|
B3 |
UART TX | A4 |
LPUART TX | |
B4 |
UART RX | A5 |
LPUART RX | |
B1 |
NWAKE | A9 |
VDD (3.3V) |
- For programming
| PAD | Description | PAD | Description | |
|---|---|---|---|---|
G5 |
NRST | G7 |
SWCLK | |
G6 |
SWDIO | G8 |
SWO |
For more information, please refer to the datasheet downloadable from the official MIPOT website.
Open STM32CubeIDE, then File --> Import
In the window that opens, select General --> Projects from Folder or Archive
Click on Directory and select the project folder, then Finish
Build the project 
.
If it becomes necessary to debug the firmware, you need to set the DEBUGGER_ON to 1 in the \Core\Inc\sys_conf.h file.
By default, it is set to 0 to reduce power consumption.
Press 
to download the firmware to the board.
LoRaMiP GUI --> DevKit
DevKit --> LoRaMiP GUI
For more information regarding the entire list of commands, please refer to the command reference downloadable from the official MIPOT website, directly in the documents section of your product. Downloading is permitted upon registration to the site.
- STM32CubeIDE
- LoRaMiP GUI (downloadable from the official MIPOT website)
- Programmer STLINK
- Serial Cable TTL-232R-3V3
Shown in the LICENSE.md file
Caution
This project is a firmware solution example on MIP Series. The main goal is to give a starting point on MIP Series Development.
Caution
This project is provided "AS IS" with no warranties.