feat(spec2026): add CPU2026 workload support

dts/xiangshan-fpga-noAIA-mem64g.dts.in

@@ -0,0 +1,174 @@
+/*
+ * XiangShan FPGA DTS used by the fpga board flow.
+ *
+ * 1. AIA is disabled, so Linux should only see the legacy CLINT + PLIC path.
+ * 2. UART16550 is exposed as the serial console.
+ */
+
+/dts-v1/;
+
+/ {
+	compatible = "freechips,rocketchip-unknown-dev";
+	model = "xiangshan,Kunminghu-dev";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <1000000>;
+
+		cpu0: cpu@0 {
+			compatible = "ICT,xiangshan", "riscv";
+			device_type = "cpu";
+			reg = <0x0>;
+			status = "okay";
+
+			d-cache-block-size = <64>;
+			d-cache-sets = <256>;
+			d-cache-size = <65536>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <48>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <256>;
+			i-cache-size = <65536>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <48>;
+			mmu-type = "riscv,sv48";
+			clock-frequency = <0>;
+			timebase-frequency = <1000000>;
+			tlb-split;
+
+			/*
+			 * Keep the Linux-friendly CPU capability description from the
+			 * workload template while using the FPGA board interrupt/peripheral
+			 * map below.
+			 */
+			riscv,isa = "rv64imafdcvh_smstateen_sscofpmf_sstc_zicntr_zihpm_svpbmt_sdtrig_smcsrind_sscsrind_svade";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions =
+				"i", "m", "a", "f", "d", "c", "v", "h",
+				"sdtrig", "sha", "shcounterenw", "shgatpa",
+				"shlcofideleg", "shtvala", "shvsatpa", "shvstvala",
+				"shvstvecd", "smcsrind", "smdbltrp",
+				"smmpm", "smnpm", "smrnmi", "smstateen",
+				"ss1p13", "ssccptr", "sscofpmf",
+				"sscounterenw", "sscsrind", "ssdbltrp", "ssnpm",
+				"sspm", "ssstateen", "ssstrict", "sstc",
+				"sstvala", "sstvecd", "ssu64xl", "supm",
+				"sv39", "sv48", "svade", "svbare", "svinval",
+				"svnapot", "svpbmt", "za64rs", "zacas", "zawrs",
+				"zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx",
+				"zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin",
+				"zic64b",
+				"ziccamoa", "ziccif", "zicclsm", "ziccrse",
+				"zicntr", "zicond", "zicsr", "zifencei",
+				"zihintntl", "zihintpause", "zihpm", "zimop",
+				"zkn", "zknd", "zkne", "zknh", "zksed",
+				"zksh", "zkt", "zvbb", "zvfh", "zvfhmin",
+				"zvkt", "zvl128b", "zvl32b", "zvl64b";
+			riscv,cbom-block-size = <0x40>;
+			riscv,cboz-block-size = <0x40>;
+
+			next-level-cache = <&l2_cache>;
+
+			intc_cpu0: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	l2_cache: l2-cache {
+		compatible = "cache";
+		cache-level = <2>;
+		cache-block-size = <64>;
+		cache-size = <1048576>;
+	};
+
+	memory: memory@80000000 {
+		device_type = "memory";
+		/*
+		 * Static 64 GiB memory profile for SPEC CPU2026 speed workloads.
+		 */
+		reg = <0x0 0x80000000 0x10 0x00000000>;
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
+		ranges;
+
+		/*
+		 * This FPGA image boots without AIA. Describe only the CLINT + PLIC
+		 * interrupt topology that the software stack should probe.
+		 */
+		clint: clint@38000000 {
+			compatible = "riscv,clint0";
+			reg = <0x0 0x38000000 0x0 0x10000>;
+			reg-names = "control";
+			interrupts-extended = <&intc_cpu0 3 &intc_cpu0 7>;
+		};
+
+		debug-controller@38020000 {
+			compatible = "sifive,debug-013", "riscv,debug-013";
+			debug-attach = "jtag";
+			reg = <0x0 0x38020000 0x0 0x1000>;
+			reg-names = "control";
+			interrupts-extended = <&intc_cpu0 65535>;
+		};
+
+		PLIC: interrupt-controller@3c000000 {
+			compatible = "riscv,plic0";
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0x0 0x3c000000 0x0 0x4000000>;
+			reg-names = "control";
+			interrupts-extended = <&intc_cpu0 11 &intc_cpu0 9>;
+			riscv,max-priority = <7>;
+			riscv,ndev = <66>;
+		};
+
+		/*
+		 * Board-specific FPGA peripheral: the external AXI UART16550 used as
+		 * the Linux console on fpga. Keep the 32-bit MMIO spacing and the
+		 * 50 MHz input clock to match the FPGA wrapper.
+		 */
+		uart0: serial@310b0000 {
+			compatible = "ns16550a";
+			reg = <0x0 0x310b0000 0x0 0x10000>;
+			reg-shift = <0x2>;
+			reg-io-width = <0x4>;
+			clock-frequency = <50000000>;
+			current-speed = <115200>;
+			//interrupt-parent = <&PLIC>;
+			//interrupts = <40>;
+			status = "okay";
+		};
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		/*
+		 * On this FPGA DTS the UART16550 interrupt is not wired into Linux
+		 * (`interrupt-parent` / `interrupts` are intentionally absent above).
+		 * `ttyS0` can still print early boot logs via polling/earlycon, but the
+		 * normal console path becomes unreliable once Linux switches away from
+		 * earlycon. When the UART interrupt is absent, use the SBI console
+		 * (`hvc0`) instead.
+		 */
+		bootargs = "console=hvc0 earlycon=sbi loglevel=8";
+		stdout-path = "serial0:115200n8";
+		linux,initrd-start = <0x0 INITRAMFS_BEGIN>;
+		linux,initrd-end = <0x0 INITRAMFS_END>;
+
+		opensbi-config {
+			compatible = "opensbi,config";
+			cold-boot-harts = <&cpu0>;
+		};
+	};
+};

dts/xiangshan-fpga-noAIA-mem8g.dts.in

@@ -89,7 +89,8 @@
 	memory: memory@80000000 {
 		device_type = "memory";
 		/*
-		 * Static 8 GiB memory profile for SPEC2017 and other large initramfs workloads.
+		 * Static 8 GiB memory profile for SPEC rate workloads and other
+		 * large initramfs images that need more than the default footprint.
 		 */
 		reg = <0x0 0x80000000 0x2 0x00000000>;
 	};

scripts/build-firmware-linux.sh

@@ -93,8 +93,7 @@ for dts_template in "$DTS_TEMPLATE_DIR"/*.dts.in ; do
     build-dtb "$dts_template"
 done
 
-# Assemble the image
-# Using `xiangshan.dtb` as the default device tree unless DEFAULT_DTB is set.
+# Assemble the image using the selected DTB basename and optional memory profile.
 if [ -n "$DTB_MEMORY_PROFILE" ]; then
     DEFAULT_DTB_BASE="$DEFAULT_DTB-mem$DTB_MEMORY_PROFILE"
 else

workloads/linux/spec2026/README.md

@@ -0,0 +1,51 @@
+# SPEC CPU2026 Linux Workload
+
+Build one case:
+
+```sh
+make linux/spec2026 BENCH=706.stockfish_r SPEC2026_ISO=/path/to/cpu2026-1.0.1.iso -jN
+```
+
+Export images:
+
+```sh
+make spec2026-images SPEC2026_ISO=/path/to/cpu2026-1.0.1.iso -jN
+```
+
+Default image export mode is `rate`. Use `MODE=speed` or `MODE=all` to
+change the selected cases.
+
+Output goes to `build/images/spec2026`.
+Rate cases are written to `build/images/spec2026rate`; speed cases are written
+to `build/images/spec2026speed`.
+
+The export tree now includes:
+
+```text
+build/images/spec2026rate/
+  bin/<case>.fw_payload.bin
+  kernel/<case>.Image
+  rootfs/<case>.rootfs.cpio
+  elf/<case>.elf
+  cmd/<case>.run.sh
+  gcpt/gcpt.elf
+  gcpt/gcpt.bin
+  cfg/<cfg>.cfg
+  logs/build_elf/<case>.log
+  stamps/<case>.images.stamp
+
+build/images/spec2026speed/
+  bin/<case>.fw_payload.bin
+  kernel/<case>.Image
+  rootfs/<case>.rootfs.cpio
+  elf/<case>.elf
+  cmd/<case>.run.sh
+  gcpt/gcpt.elf
+  gcpt/gcpt.bin
+  cfg/<cfg>.cfg
+  logs/build_elf/<case>.log
+  stamps/<case>.images.stamp
+```
+
+Re-running `make spec2026-images` skips completed cases and resumes an
+interrupted case build through `build/linux-workloads/spec2026/_bench-builds`.

workloads/linux/spec2026/build.sh

@@ -0,0 +1,49 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+: "${SPEC2026_CASE:?SPEC2026_CASE is required}"
+: "${SPEC2026:?SPEC2026 is required}"
+: "${SPEC2026_CFG:?SPEC2026_CFG is required}"
+: "${CROSS_COMPILE:=riscv64-unknown-linux-gnu-}"
+: "${SPEC2026_TUNE:=base}"
+: "${SPEC2026_JOBS:=$(nproc)}"
+: "${SPEC2026_ELF_ONLY:=false}"
+: "${SPEC2026_LOG_DIR:=$WORKLOAD_BUILD_DIR/logs}"
+: "${PKG_DIR:=$WORKLOAD_BUILD_DIR/package}"
+
+mkdir -p "$SPEC2026_LOG_DIR"
+
+spec2026_progress_prefix() {
+  local k="${SPEC2026_PROGRESS_K:-1}"
+  local n="${SPEC2026_PROGRESS_N:-1}"
+  printf '[spec2026 %s/%s]' "$k" "$n"
+}
+
+status() {
+  printf '%s %s\n' "$(spec2026_progress_prefix)" "$*"
+}
+
+is_true() {
+  case "$1" in
+    1|true|yes|on) return 0 ;;
+    *) return 1 ;;
+  esac
+}
+
+python_args=()
+if is_true "$SPEC2026_ELF_ONLY"; then
+  python_args+=(--elf-only)
+fi
+
+python3 "$WORKLOAD_DIR/spec2026-package.py" \
+  --case "$SPEC2026_CASE" \
+  --spec "$SPEC2026" \
+  --spec-config "$SPEC2026_CFG" \
+  --pkg-dir "$PKG_DIR" \
+  --out-dir "$WORKLOAD_BUILD_DIR" \
+  --cross-compile "$CROSS_COMPILE" \
+  --log-dir "$SPEC2026_LOG_DIR" \
+  --tune "$SPEC2026_TUNE" \
+  --jobs "$SPEC2026_JOBS" \
+  --input-set "${SPEC2026_INPUT:-ref}" \
+  "${python_args[@]}"

workloads/linux/spec2026/prepare-spec-workspace.sh

@@ -0,0 +1,56 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+source_spec_iso="$(realpath "$1")"
+prepared_spec_root="$(realpath -m "$2")"
+
+prepare_dir="$(dirname "$prepared_spec_root")"
+mkdir -p "$prepare_dir"
+chmod -R u+rwX "$prepared_spec_root" 2>/dev/null || true
+rm -rf "$prepared_spec_root"
+
+temp_root=""
+cleanup() {
+  if [ -n "$temp_root" ]; then
+    chmod -R u+rwX "$temp_root" 2>/dev/null || true
+    rm -rf "$temp_root" 2>/dev/null || true
+  fi
+}
+trap cleanup EXIT
+
+if ! command -v xorriso >/dev/null 2>&1; then
+  echo "xorriso is required to extract $source_spec_iso" >&2
+  exit 1
+fi
+
+tmp_parent="${SPEC2026_PREPARE_TMPDIR:-${TMPDIR:-/tmp}}"
+mkdir -p "$tmp_parent"
+temp_root="$(mktemp -d "$tmp_parent/spec2026-prepare.XXXXXX")"
+
+media_root="$temp_root/media"
+staged_spec_root="$temp_root/spec-src"
+mkdir -p "$media_root"
+
+xorriso -osirrox on -indev "$source_spec_iso" -extract / "$media_root" >/dev/null
+
+if ! [ -f "$media_root/install.sh" ]; then
+  echo "install.sh not found in $source_spec_iso" >&2
+  exit 1
+fi
+
+(
+  cd "$media_root"
+  env -u SPEC sh ./install.sh -f -d "$staged_spec_root"
+)
+
+mkdir -p "$prepared_spec_root"
+cp -R "$staged_spec_root"/. "$prepared_spec_root"/
+chmod -R u+rwX "$prepared_spec_root"
+
+if [ -x "$prepared_spec_root/bin/relocate" ]; then
+  (
+    cd "$prepared_spec_root"
+    . ./shrc >/dev/null
+    bin/relocate >/dev/null
+  )
+fi