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Merged
PeterMonsson merged 1 commit into from
Jan 7, 2026
Merged

Rename uvmkit_check to uvmkit_assert #17

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50 changes: 25 additions & 25 deletions CLAUDE.md
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ This file provides guidance to Claude Code (claude.ai/code) when working with co

## Project Overview

**uvmkit_check** is a SystemVerilog assertion library inspired by JUnit Assert. It provides a comprehensive set of macros for validating test conditions in verification environments, supporting both UVM and non-UVM workflows across multiple simulators.
**uvmkit_assert** is a SystemVerilog assertion library inspired by JUnit Assert. It provides a comprehensive set of macros for validating test conditions in verification environments, supporting both UVM and non-UVM workflows across multiple simulators.

### Design Philosophy

Expand All @@ -18,7 +18,7 @@ This file provides guidance to Claude Code (claude.ai/code) when working with co

### Core Components

#### 1. Configuration Layer (`src/uvmkit_check.sv` lines 1-98)
#### 1. Configuration Layer (`src/uvmkit_assert.sv` lines 1-98)

**Purpose**: Provides customizable infrastructure for error reporting and stacktraces.

Expand All @@ -29,7 +29,7 @@ This file provides guidance to Claude Code (claude.ai/code) when working with co

**Design Pattern**: Uses `ifndef` guards to allow external overrides for testing and simulator customization.

#### 2. Assertion Groups (`src/uvmkit_check.sv` lines 100-628)
#### 2. Assertion Groups (`src/uvmkit_assert.sv` lines 100-628)

Organized by functionality (mirroring JUnit organization):

Expand All @@ -47,7 +47,7 @@ Organized by functionality (mirroring JUnit organization):

**Design Pattern**: Each macro follows this structure:
```systemverilog
`define uvmkit_check_<name>(<params>, msg="") \
`define uvmkit_assert_<name>(<params>, msg="") \
begin \
// 1. Declare automatic variables for evaluation
// 2. Evaluate expressions once (avoid multiple evaluation side effects)
Expand Down Expand Up @@ -76,7 +76,7 @@ The library uses preprocessor directives to adapt to different environments:

### Testing Infrastructure

#### Unit Tests (`tests/unit/uvmkit_check_unit_test.sv`)
#### Unit Tests (`tests/unit/uvmkit_assert_unit_test.sv`)

**Strategy**: Override `uvmkit_error_msg` to capture errors for validation.

Expand All @@ -89,16 +89,16 @@ string last_msg;
error_called = 1; \
last_msg = msg;

`include "uvmkit_check.sv"
`include "uvmkit_assert.sv"

// Test both success and failure paths
`SVTEST(test_check_equals)
error_called = 0;
`uvmkit_check_equals(5, 5, "should pass")
`uvmkit_assert_equals(5, 5, "should pass")
`FAIL_IF(error_called) // Success: no error

error_called = 0;
`uvmkit_check_equals(5, 3, "should fail")
`uvmkit_assert_equals(5, 3, "should fail")
`FAIL_UNLESS(error_called) // Failure: error called
`SVTEST_END
```
Expand Down Expand Up @@ -155,9 +155,9 @@ This project follows **Natural Docs** style, similar to UVM documentation:
### Code Style

#### Macro Naming Convention
- Prefix: `uvmkit_check_`
- Format: `uvmkit_check_<operation>[_<type>]`
- Examples: `uvmkit_check_equals`, `uvmkit_check_equals_real`, `uvmkit_check_equals_uvm`
- Prefix: `uvmkit_assert_`
- Format: `uvmkit_assert_<operation>[_<type>]`
- Examples: `uvmkit_assert_equals`, `uvmkit_assert_equals_real`, `uvmkit_assert_equals_uvm`

#### Internal Variables
- Prefix with underscore: `_exp_result`, `_a_str`
Expand Down Expand Up @@ -202,7 +202,7 @@ runSVUnit -c -Wno-WIDTH -o obj_dir \

```systemverilog
//------------------------------------------------------------------------------
// Macro: uvmkit_check_range
// Macro: uvmkit_assert_range
//
// Asserts that a value falls within a specified range [min, max] inclusive.
//
Expand All @@ -213,16 +213,16 @@ runSVUnit -c -Wno-WIDTH -o obj_dir \
// msg - Optional message providing context (default: "")
//
// Example:
// | `uvmkit_check_range(temperature, -40, 125, "Temperature out of spec")
// | `uvmkit_check_range(count, 0, 100, "Count must be 0-100")
// | `uvmkit_assert_range(temperature, -40, 125, "Temperature out of spec")
// | `uvmkit_assert_range(count, 0, 100, "Count must be 0-100")
//
`define uvmkit_check_range(value, min, max, msg="") \
`define uvmkit_assert_range(value, min, max, msg="") \
begin \
automatic int _value = value; \
automatic int _min = min; \
automatic int _max = max; \
if (_value < _min || _value > _max) begin \
`uvmkit_error_msg_fmt("uvmkit_check_range", \
`uvmkit_error_msg_fmt("uvmkit_assert_range", \
$sformatf("Expected '%s' (%0d) to be in range [%0d, %0d]", \
`"value`", _value, _min, _max), msg) \
end \
Expand Down Expand Up @@ -288,13 +288,13 @@ Examples:

**Problem**: Floating-point precision makes exact equality unreliable.

**Solution**: Always use `uvmkit_check_equals_real` with appropriate delta:
**Solution**: Always use `uvmkit_assert_equals_real` with appropriate delta:
```systemverilog
// Bad
`uvmkit_check_equals(voltage, 3.3, "voltage check") // Don't do this with reals
`uvmkit_assert_equals(voltage, 3.3, "voltage check") // Don't do this with reals

// Good
`uvmkit_check_equals_real(3.3, voltage, 0.01, "voltage check")
`uvmkit_assert_equals_real(3.3, voltage, 0.01, "voltage check")
```

## Build System
Expand Down Expand Up @@ -333,8 +333,8 @@ Examples:
### Potential Additions

1. **Array Assertions**
- `uvmkit_check_array_equals`
- `uvmkit_check_array_contains`
- `uvmkit_assert_array_equals`
- `uvmkit_assert_array_contains`

2. **Size Information in Errors**
- Show bit widths when X-value comparisons fail
Expand All @@ -345,7 +345,7 @@ Examples:
- User-configurable via macro override

4. **Performance Assertions**
- `uvmkit_check_time_limit` - Execution time bounds
- `uvmkit_assert_time_limit` - Execution time bounds
- Cycle count validation

5. **Coverage Integration**
Expand All @@ -361,8 +361,8 @@ Examples:

### Internal Documentation
- `README.md` - User-facing documentation
- `src/uvmkit_check.sv` - Source code with Natural Docs comments
- `tests/unit/uvmkit_check_unit_test.sv` - Test examples
- `src/uvmkit_assert.sv` - Source code with Natural Docs comments
- `tests/unit/uvmkit_assert_unit_test.sv` - Test examples

## Debugging Tips

Expand All @@ -382,7 +382,7 @@ string captured_errors[$];
`define uvmkit_error_msg(typ, msg) \
captured_errors.push_back($sformatf("[%s] %s", typ, msg));

`include "uvmkit_check.sv"
`include "uvmkit_assert.sv"

// Now all errors are captured in captured_errors queue
```
Expand Down
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