Perf/fix4b lds linesearch jv jaref cache#82
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Replace per-lane HBM reads of efc_force in the J^T@efc_force inner loop with cooperative LDS fills during Phase 4a, then fast LDS reads in Phase 4b. The 8 lanes per env already write efc_force to HBM in COOP-strided order during Phase 4a. This patch stores efc_val into efc_force_lds at the same time (while the value is hot in registers), then Phase 4b reads from LDS instead of HBM for the inner j_c accumulation loop. LDS budget: (ENVS=8, MAX_CON=64) float32 = 2 KB, well within the 64 KB per-workgroup LDS limit on gfx942. No VGPR overhead vs the HBM path. Why LDS over register cache (Fix-4b): - Register cache consumed 8*8=64 VGPRs per lane, hurting occupancy on MI325X - LDS cache uses shared on-chip memory with zero VGPR cost - LDS latency (~100 cycles) vs HBM (~600 cycles) still gives significant speedup - Tail path handles n_con > 64 via HBM fallback (uncommon on humanoid robots) Correctness: efc_force_lds is filled before the existing block.sync() that Phase 4b already depends on, so no additional synchronization is needed.
Cache constraint arrays (Jaref, jv, efc_D, efc_frictionloss, diag) in LDS at the start of _func_ls_pt_opt_twc. This function is called up to ls_iterations times per CG step, reading these n_con arrays from HBM on every call. Moving them to LDS eliminates the repeated HBM traffic. LDS budget: 5 * ENVS(8) * MAX_CON(64) = 2560 floats = 10 KB. Total LDS with prior caches (Phase 4b efc_force): ~14 KB of 64 KB max. Cooperative fill: each lane fills its COOP-strided slice before the constraint loops begin (1 block.sync()). Tail path falls back to HBM for n_con > 64 (uncommon on humanoid robots with typical contact counts). This patch stacks on top of the Phase 4b efc_force LDS cache (perf/fix4b-lds-efc-force-cache-tiled-wc-v2).
…ath to 200%) Stacks four independent optimizations on top of the Phase 4b efc_force LDS cache: 1. LDS-cache Jaref/jv/efc_D in _func_ls_pt_opt_twc and _func_ls_pt_3a_twc: These functions are called up to ls_iterations times per CG step, reading n_con arrays from HBM on every call. Moving them to LDS eliminates repeated HBM round-trips. LDS budget: 5 arrays * ENVS(8) * 64 = 10 KB. 2. fn_attrs(1,1) on _kernel_solve_body_tiled_wc_amdgpu: Removes JIT default "1,2" max waves/EU constraint. Kernel exceeds 256 VGPRs so "1,2" wastes compiler effort on VGPR compression without any occupancy benefit. Setting "1,1" lets compiler allocate VGPRs freely. 3. perf_dispatch interval 5s -> 3600s on func_solve_body: Eliminates periodic re-benchmarking overhead during production runs. 4. Occupancy tuning for multicontact narrowphase (AMD only): CU multiplier 256->64 and max_items_per_thread 128->512 for better GPU utilization. block_dim=64 on func_collision_clear for wave64 alignment.
qd.static(N) cannot be used as SharedArray dimension inside @qd.func. Replace LS_MAX_CON/LS3A_MAX_CON qd.static locals with module-level _LS_MAX_CON/_LS3A_MAX_CON constants (same pattern as _TWC_BLOCK_DIM).
- Remove pt_3a LDS optimization (Jaref3_lds undeclared, causes NameError) - Fix pt_opt fill loop: replace "while A and B" with "while A: if B:" pattern - Retain: pt_opt LDS cache, fn_attrs(1,1), perf_dispatch 3600s, CU tuning
Quadrants @qd.func/@qd.kernel do not support "while A and B" syntax. Replace all occurrences with "while A: if B:" pattern. Affects: _func_ls_pt_opt_twc fill loop and Phase 4b LDS accumulation loop.
Quadrants @qd.func cannot reference module-level Python variable names as loop bounds or SharedArray dimensions - use integer literals directly. Replace all _LS_MAX_CON with 64 in _func_ls_pt_opt_twc.
…adrants whl) fn_attrs dict syntax not supported by local quadrants 0.0.0 whl. Keep only: LDS cache for pt_opt, perf_dispatch 3600s, CU tuning.
…func_ls_pt_opt_twc
…fc_force LDS from PR#81
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Resolves Genesis-Embodied-AI/Genesis#
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