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Create compatibility module with tests
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
1 parent f619454 commit 039cee9

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7 files changed

+194
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.travis.yml

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script:
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- cd tests && python3 -m unittest test.TestRTLIL
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- stage: Tests
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name: "Test compatibility package"
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script:
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- cd tests && python3 -m unittest test.TestCompat
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- stage: Build
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name: "Build"
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script:

Makefile

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clean: version-clean
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# Build and upload commands
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# Build and upload main package
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#PYPI_TEST = --repository-url https://test.pypi.org/legacy/
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PYPI_TEST = --repository testpypi
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build: $(VERSION_PY) | $(CONDA_ENV_PYTHON)
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$(IN_CONDA_ENV) python setup.py sdist bdist_wheel && twine check dist/*
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.PHONY: build
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build-clean:
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rm -rf env/downloads/conda-pkgs
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rm -rf build dist *.egg-info
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find -name *.pyc -delete
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find -name __pycache__ -delete
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clean: build-clean
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#PYPI_TEST = --repository-url https://test.pypi.org/legacy/
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#PYPI_TEST = --repository testpypi
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upload-test: build | $(CONDA_ENV_PYTHON)
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$(IN_CONDA_ENV) twine upload ${PYPI_TEST} dist/*
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.PHONY: upload-test
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upload: build | $(CONDA_ENV_PYTHON)
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$(IN_CONDA_ENV) twine upload --verbose dist/*
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.PHONY: upload
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.PHONY: build build-clean upload upload-test
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# Build and upload compatibility package
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COMPAT_PACKAGE_DIR = compat
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build_compat: $(VERSION_PY) | $(CONDA_ENV_PYTHON)
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$(IN_CONDA_ENV) cd $(COMPAT_PACKAGE_DIR); python setup.py sdist bdist_wheel && twine check dist/*
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build_compat-clean:
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cd $(COMPAT_PACKAGE_DIR); rm -rf env/downloads/conda-pkgs
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cd $(COMPAT_PACKAGE_DIR); rm -rf build dist *.egg-info
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cd $(COMPAT_PACKAGE_DIR); find -name *.pyc -delete
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cd $(COMPAT_PACKAGE_DIR); find -name __pycache__ -delete
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upload_compat-test: build_compat | $(CONDA_ENV_PYTHON)
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$(IN_CONDA_ENV) cd $(COMPAT_PACKAGE_DIR); twine upload ${PYPI_TEST} dist/*
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upload_compat: build_compat | $(CONDA_ENV_PYTHON)
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$(IN_CONDA_ENV) cd $(COMPAT_PACKAGE_DIR); twine upload --verbose dist/*
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.PHONY: build_compat build_compat-clean upload_compat-test upload_compat
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# Tests
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test: $(VERSION_PY) | $(CONDA_ENV_PYTHON)
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$(IN_CONDA_ENV) cd docs; make html
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$(IN_CONDA_ENV) cd tests; make test
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.PHONY: test
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# Cleanup
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clean: build-clean build_compat-clean

compat/setup.py

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#!/usr/bin/env python
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2020 The SymbiFlow Authors.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# https://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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import sys
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from os import path
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from setuptools import setup, find_packages
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__dir__ = path.dirname(path.abspath(__file__))
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readme_file = path.join(__dir__, '../README.rst')
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try:
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with open(readme_file) as f:
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readme = f.read()
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except FileNotFoundError as e:
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import traceback
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traceback.print_exc()
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readme = ''
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__version__ = 'error'
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install_requires = [
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'sphinxcontrib-hdl-diagrams'
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]
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setup(
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name='sphinxcontrib-verilog-diagrams',
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version="0.1.0",
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description='Generate diagrams from Verilog in Sphinx.',
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long_description=readme,
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long_description_content_type="text/x-rst",
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author="The SymbiFlow Authors",
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author_email='symbiflow@lists.librecores.org',
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url='https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams',
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packages=find_packages(),
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license="Apache 2.0",
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keywords='Verilog sphinx sphinx-extension netlistsvg FPGA',
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classifiers=[
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'Development Status :: 4 - Beta',
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'Framework :: Sphinx :: Extension',
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'Intended Audience :: Developers',
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'License :: OSI Approved :: Apache Software License',
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'Natural Language :: English',
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'Programming Language :: Python :: 3.5',
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'Programming Language :: Python :: 3.6',
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'Topic :: Text Processing',
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],
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install_requires=install_requires,
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)
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import sphinxcontrib_hdl_diagrams
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def setup(app):
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print("")
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print("WARNING:")
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print(" sphinxcontrib-verilog-diagram extension is depreciated!")
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print(" Please use sphinxcontrib-hdl-diagrams instead:")
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print(" https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams")
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print("")
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return sphinxcontrib_hdl_diagrams.setup(app)

environment.yml

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- -r file:requirements.txt
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- -r file:docs/requirements.txt
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- .
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- compat/.

tests/test.py

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app = Sphinx(buildername="html", warningiserror=True, **sphinx_dirs)
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app.build(force_all=True)
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class TestCompat(TestBase):
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TEST_CASE_NAME = "TestCompat"
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TEST_CASE_BUILD_DIR = os.path.join("build", TEST_CASE_NAME)
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def test_yosys_script(self):
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TEST_NAME = "test_compat"
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TEST_BUILD_DIR = os.path.join("build", self.TEST_CASE_NAME, TEST_NAME)
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TEST_FILES = [
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"test_compat/test_compat.rst",
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"code/verilog/adder.v"
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]
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TEST_JINJA_DICT = {
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"hdl_diagrams_path": "'{}'".format(HDL_DIAGRAMS_PATH),
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"master_doc": "'test_compat'",
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"custom_variables": """
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extensions = [
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'sphinxcontrib_verilog_diagrams',
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]"""
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}
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self.prepare_test(TEST_NAME, TEST_BUILD_DIR, TEST_FILES, **TEST_JINJA_DICT)
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# Run the Sphinx
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sphinx_dirs = get_sphinx_dirs(TEST_BUILD_DIR)
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with docutils_namespace():
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app = Sphinx(buildername="html", warningiserror=True, **sphinx_dirs)
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app.build(force_all=True)
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if __name__ == '__main__':
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unittest.main()

tests/test_compat/test_compat.rst

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Test Compatibility Package
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==========================
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This test checks whether the ``sphinxcontrib-verilog-diagrams`` compatibility
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package works as intended.
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Here is the fragment of the ``conf.py`` script, used to configure the extension::
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extensions = [
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'sphinxcontrib_verilog_diagrams',
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]
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Yosys BlackBox Diagram
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----------------------
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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.. verilog-diagram:: adder.v
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:type: yosys-blackbox
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:module: ADDER
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Yosys AIG Diagram
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-----------------
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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.. verilog-diagram:: adder.v
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:type: yosys-aig
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:module: ADDER
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Netlistsvg Diagram
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------------------
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.. code-block:: rst
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.. verilog-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER
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.. verilog-diagram:: adder.v
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:type: netlistsvg
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:module: ADDER

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