Lpm update #610
Lpm update #610
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uditkumarti
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| 1. Only A core as suspend master supported and tested with Linux. | ||
| 2. The LPM feature is not supported on HS-SE variant J784S4. | ||
| 3. If PCIe is being used, the resume latency increases by 1 sec for every PCIe instance, If EP is not connected. |
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EP?.. Is it better to have this as Endpoint, wouldn't it be confusing EP alone ?
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EP is standard term
| 2. The LPM feature is not supported on HS-SE variant J784S4. | ||
| 3. If PCIe is being used, the resume latency increases by 1 sec for every PCIe instance, If EP is not connected. | ||
| 4. Remote core firmwares are getting loaded by Linux on resume. | ||
| 5. MCU domain R5 core, cannot be used in split mode. |
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This core cannot be used in split mode only to exercise LPM sequence correct ? So, isn't this a known issue rather than limitation.
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Its limitation rather than issue
| Software modifications | ||
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| TI’s K3 Jacinto family of SOCs have a concept of boardcfg that can be used to configure certain parameters at build time. | ||
| By default, SDK supports SOC_OFF mode. |
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By default, SDK supports SOC_OFF mode.
SDK supports both, but SOC_OFF is enabled/selected by default. So, may be something like below
By default, SOC_OFF mode enabled by default in SDK.
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will do this change . Thanks
Add flow diagram, hardware details to excercise LPM mode. Signed-off-by: Udit Kumar <u-kumar1@ti.com>
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Nitpick: Let's use IO_RET everywhere and not IO-RET in this pic.
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Let's use "Decrypt"
| run application. | ||
| However, it is desired to run application use cases within 2-3 seconds of power on, for this purpose there are many custom | ||
| optimizations done, which are not scalable from platform to platform. | ||
| LPM saves partially SW state to DDR which helps in achieving faster boot. |
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thanks will reword
In LPM state, partial SW state is saved to DDR which helps in achieving faster boot
| | | I/O | | | | | ||
| +---------------------+---------------+---------------+-------------------------+-----------------------+ | ||
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| Based upon, requirement of on power consumption and latency (the time it takes to wake-up to Active mode). |
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Based upon the requirement of power consumption and latency (the time it takes to wake-up to Active mode),
users can select the appropriate low power mode at build time to fit the needs of their application.
The default mode in the SDK is SOC OFF.
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| LPM entry overview | ||
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| After detecting condition to enter into standby, Application shall close all applications interacting with |
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This part is not clear to me. Which application is closing all applications ? Is it the kernel closing all the user space applications including the ones interacting with remote firmware ?
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Normally its power monitor thread, But will reword to below
After detecting the condition to enter standby, applications interacting with remote firmware shall be closed
before entering standby.
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| In above board config file, default lpm_mode is 0x5 (SOC_OFF) and suspend_initiator is 0xA (A72_0 host). | ||
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| To set the LPM mode as IO_RET_PLUS_DDR. Change lpm_mode to 0x2 |
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To set the LPM mode as IO_RET_PLUS_DDR, change lpm_mode to 0x2
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| On receiving wakeup trigger, PMIC will restore power to SOC and SOC resume process will exit DDR from self-refresh mode and restore the | ||
| saved software context. | ||
| As part of resume process, firmwares of remote cores will be reloaded, Therefore application interacting with remote firmware shall be started again. |
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| LPM exit overview | ||
| ----------------- | ||
| On receiving wakeup trigger, PMIC will restore power to SOC and SOC resume process will exit DDR from self-refresh mode and restore the |
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Throughout the document, I see SOC and SoC being mixed. The latter is the right one to use.
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Ack for this PR.
But in general this need fix in throughout whole repo
| .. ifconfig:: CONFIG_part_variant in ('J7200') | ||
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| By default, SOC_OFF mode can be validated on J7200 EVM without any hardware changes. | ||
| In case IO_ONLY_PLUS_DDR needs to be tested user needs to do the following board modification. These modifications will not impact SOC_OFF mode. |
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In case IO_ONLY_PLUS_DDR mode needs to be tested,user needs to do the following board modification.
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There are also vale comments and unnecessary unicode characters that need to be addressed.
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| Hardware modifications | ||
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