Update `output_to_verilog` to inline temporary wires, using `GateGraph`:#471

Merged

fdxmw merged 7 commits into

UCSBarchlab:developmentfrom

Jul 25, 2025

Commits on Jul 23, 2025

Update `output_to_verilog` to inline temporary wires, using `GateGraph`:
fdxmw
committed

Commits on Jul 24, 2025

Improve Verilog identifier naming, fix two bugs, add tests, refactor duplicated
fdxmw
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Fix some pre-existing bugs:
fdxmw
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Update _NameSanitizer to try appending the current internal_index before generating an entirely new name. Fix a bug where a generated name could collide with an identifier name. Add tests.
fdxmw
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Improve Verilog output by using sanitized MemBlock and RomBlock names instead
fdxmw
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Minor Verilog output improvements: Move lines with only "begin" to the end of previous line, remove an unnecessary begin/end block, put "end else begin" on the same line.
fdxmw
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Commits on Jul 25, 2025

Clean up `output_to_verilog`'s newline logic. This simplifies the code and removes an unnecessary blank line from the generated output.
fdxmw
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