Add Zbs instruction testbench with assertions and randomized tests#210
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Dazhou-20383 wants to merge 4 commits intozbs-implementationfrom
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Add Zbs instruction testbench with assertions and randomized tests#210Dazhou-20383 wants to merge 4 commits intozbs-implementationfrom
Dazhou-20383 wants to merge 4 commits intozbs-implementationfrom
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🔧 DE1-SoC Synthesis Report Summary Diff📊 Fitter Summary (.fit.summary)@@ -1,4 +1,4 @@
-Fitter Status : Successful - Sun Mar 22 02:17:43 2026
+Fitter Status : Successful - Sun Mar 22 17:42:58 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : utoss-risc-v
Top-level Entity Name : top⏱️ Timing Analysis Summary (.sta.summary)No changes detected Comparing synthesis results from main branch vs. this PR |
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Features:
• Assertion-based verification for all four instructions: bclr, bset, binv, bext.
• Corner case tests for bit 0 (LSB) and bit 31 (MSB).
• Randomized testing to validate instruction behavior across a wide range of inputs.
• Reusable run_test() task structure for clean and modular testing.
Notes:
• This branch contains only the testbench commit (zbs_tb.sv).
• Any previous .DS_Store changes are excluded.
• This PR supersedes the previous accidental commit of the testbench to main, ensuring proper branch-based review.