Separate port and generic formals

Author: kraigher

vhdl_lang/src/analysis/concurrent.rs

@@ -198,16 +198,16 @@ impl<'a> AnalyzeContext<'a> {
                             )?;
 
                             if let NamedEntityKind::Entity(ent_region) = ent.kind() {
-                                let formal_region = ent_region.to_entity_formal();
+                                let (generic_region, port_region) = ent_region.to_entity_formal();
 
                                 self.analyze_assoc_elems_with_formal_region(
-                                    &formal_region,
+                                    &generic_region,
                                     parent,
                                     &mut instance.generic_map,
                                     diagnostics,
                                 )?;
                                 self.analyze_assoc_elems_with_formal_region(
-                                    &formal_region,
+                                    &port_region,
                                     parent,
                                     &mut instance.port_map,
                                     diagnostics,
@@ -235,15 +235,15 @@ impl<'a> AnalyzeContext<'a> {
                             )?;
 
                             if let NamedEntityKind::Component(ent_region) = ent.kind() {
-                                let formal_region = ent_region.to_entity_formal();
+                                let (generic_region, port_region) = ent_region.to_entity_formal();
                                 self.analyze_assoc_elems_with_formal_region(
-                                    &formal_region,
+                                    &generic_region,
                                     parent,
                                     &mut instance.generic_map,
                                     diagnostics,
                                 )?;
                                 self.analyze_assoc_elems_with_formal_region(
-                                    &formal_region,
+                                    &port_region,
                                     parent,
                                     &mut instance.port_map,
                                     diagnostics,

vhdl_lang/src/analysis/formal_region.rs

@@ -6,10 +6,13 @@
 
 use std::sync::Arc;
 
-use crate::{ast::Designator, Diagnostic, SrcPos};
+use crate::{
+    ast::{Designator, ObjectClass},
+    Diagnostic, SrcPos,
+};
 
 use super::{
-    region::{NamedEntityKind, Object, Type, TypeEnt},
+    region::{NamedEntityKind, Object, TypeEnt},
     NamedEntity,
 };
 
@@ -40,11 +43,17 @@ impl InterfaceEnt {
         }
     }
 
+    pub fn is_signal(&self) -> bool {
+        match self.ent.kind() {
+            NamedEntityKind::Object(obj) => obj.class == ObjectClass::Signal,
+            _ => false,
+        }
+    }
+
     pub fn base_type(&self) -> &TypeEnt {
         match self.ent.kind() {
             NamedEntityKind::Object(obj) => obj.subtype.base_type(),
             NamedEntityKind::InterfaceFile(file_type) => file_type.base_type(),
-            NamedEntityKind::Type(Type::Subtype(subtype)) => subtype.base_type(),
             _ => {
                 unreachable!();
             }

vhdl_lang/src/analysis/region.rs

@@ -253,19 +253,26 @@ impl<'a> Region<'a> {
         self
     }
 
-    pub fn to_entity_formal(&self) -> FormalRegion {
+    pub fn to_entity_formal(&self) -> (FormalRegion, FormalRegion) {
         // @TODO separate generics and ports
-        let mut entities = Vec::with_capacity(self.entities.len());
+        let mut generics = Vec::with_capacity(self.entities.len());
+        let mut ports = Vec::with_capacity(self.entities.len());
+
         for ent in self.entities.values() {
             if let NamedEntities::Single(ent) = ent {
                 if let Some(ent) = InterfaceEnt::from_any(ent.clone()) {
-                    entities.push(ent);
+                    if ent.is_signal() {
+                        ports.push(ent);
+                    } else {
+                        generics.push(ent);
+                    }
                 }
             }
         }
         // Sorting by source file position gives declaration order
-        entities.sort_by_key(|ent| ent.decl_pos().map(|pos| pos.range().start));
-        FormalRegion::new(entities)
+        generics.sort_by_key(|ent| ent.decl_pos().map(|pos| pos.range().start));
+        ports.sort_by_key(|ent| ent.decl_pos().map(|pos| pos.range().start));
+        (FormalRegion::new(generics), FormalRegion::new(ports))
     }
 
     pub fn extend(region: &'a Region<'a>, parent: Option<&'a Region<'a>>) -> Region<'a> {

vhdl_lang/src/analysis/tests/association_formal.rs

@@ -150,6 +150,48 @@ end architecture;
     );
 }
 
+#[test]
+fn does_not_mixup_ports_and_generics() {
+    let mut builder = LibraryBuilder::new();
+    let code = builder.code(
+        "libname",
+        "
+entity ent_inst is
+    generic (
+        thegeneric : boolean 
+    );
+    port (
+        theport : in boolean 
+    );
+end entity;
+
+architecture a of ent_inst is
+begin
+end architecture;
+
+entity ent is
+end entity;
+
+architecture a of ent is
+   signal sig : boolean;
+begin
+   ent: entity work.ent_inst
+       generic map (theport => sig)
+       port map (thegeneric => 0);
+end architecture;
+        ",
+    );
+
+    let diagnostics = builder.analyze();
+    check_diagnostics(
+        diagnostics,
+        vec![
+            Diagnostic::error(code.s("theport", 2), "No declaration of 'theport'"),
+            Diagnostic::error(code.s("thegeneric", 2), "No declaration of 'thegeneric'"),
+        ],
+    );
+}
+
 #[test]
 fn resolve_port_and_surrounding_name() {
     let mut builder = LibraryBuilder::new();