Suite update - Added designs (Vortex, NVDLA, coralnpu), changed suite update logic

.claude/skills/new-design/SKILL.md

@@ -41,25 +41,8 @@ The setup.sh must install all dependencies needed to convert the source HDL to p
 
 ### 4. Create `designs/src/$0/verilog.mk`
 
-This file controls RTL selection between dev-generated and release Verilog. Use one of these patterns:
+This file controls RTL selection, freeing up clutter in per-technology `config.mk` files.
 
-**Simple single-file design:**
-```makefile
-ifneq ($(wildcard $(DEV_FLAG)),)
-export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$0/dev/generated/$0.v
-else
-export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$0/$0.v
-endif
-```
-
-**Multi-file design (wildcard):**
-```makefile
-ifneq ($(wildcard $(DEV_FLAG)),)
-export VERILOG_FILES = $(wildcard $(BENCH_DESIGN_HOME)/src/$0/dev/repo/rtl/*.v)
-else
-export VERILOG_FILES = $(wildcard $(BENCH_DESIGN_HOME)/src/$0/*.v)
-endif
-```
 
 ### 5. Identify and create FakeRAM black-box memories
 

.github/workflows/require-design-files.yml

@@ -0,0 +1,164 @@
+name: Validate PR designs
+
+on:
+  pull_request:
+    types: [opened, synchronize, reopened, ready_for_review]
+    paths:
+      - "designs/**"
+
+permissions:
+  contents: read
+
+jobs:
+  validate:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          fetch-depth: 0
+
+      - name: Validate required design files
+        shell: bash
+        run: |
+          set -euo pipefail
+
+          BASE_REF="origin/${{ github.base_ref }}"
+          HEAD_SHA="${{ github.sha }}"
+          git fetch origin "${{ github.base_ref }}" --no-tags --prune
+
+          techs=(sky130hd asap7 nangate45)
+
+          # Collect changed file paths for A/M (and treat R* as changed using new path field).
+          mapfile -t changed_paths < <(
+            git diff --name-status "${BASE_REF}...${HEAD_SHA}" \
+              | awk '
+                  $1=="A" || $1=="M" {print $2}
+                  $1 ~ /^R/ {print $3}
+                '
+          )
+
+          relevant_paths=()
+          for p in "${changed_paths[@]}"; do
+            if [[ "$p" =~ ^designs/src/[^/]+/ ]] || [[ "$p" =~ ^designs/[^/]+/[^/]+/ ]]; then
+              relevant_paths+=("$p")
+            fi
+          done
+
+          if (( ${#relevant_paths[@]} == 0 )); then
+            echo "No changes to designs/src/<design>/ or designs/<tech>/<design>/. Nothing to validate."
+            exit 0
+          fi
+
+          declare -A touched_src_design=()     # key: <design>
+          declare -A touched_tech_design=()    # key: <tech>/<design>
+
+          for p in "${changed_paths[@]}"; do
+            if [[ "$p" =~ ^designs/src/([^/]+)/ ]]; then
+              touched_src_design["${BASH_REMATCH[1]}"]=1
+              continue
+            fi
+
+            if [[ "$p" =~ ^designs/([^/]+)/([^/]+)/ ]]; then
+              t="${BASH_REMATCH[1]}"
+              d="${BASH_REMATCH[2]}"
+              for allowed in "${techs[@]}"; do
+                if [[ "$t" == "$allowed" ]]; then
+                  touched_tech_design["$t/$d"]=1
+                  break
+                fi
+              done
+            fi
+          done
+
+          echo "Design's with new or updated designs/src/ files:"
+          if (( ${#touched_src_design[@]} == 0 )); then
+            echo " - (none)"
+          else
+            for d in "${!touched_src_design[@]}"; do echo " - $d"; done
+          fi
+
+          echo "Design's with new/updated designs/<tech>/ files:"
+          if (( ${#touched_tech_design[@]} == 0 )); then
+            echo " - (none)"
+          else
+            for td in "${!touched_tech_design[@]}"; do echo " - $td"; done
+          fi
+
+          # REQUIRED files relative to designs/src/<design>/
+          required_src=(
+            "file:verilog.mk"
+            "file:LICENSE"
+            "dir:dev"
+          )
+
+          # REQUIRED files relative to designs/<tech>/<design>/
+          # Both config.mk and constraint.sdc are checked recursively (see below),
+          # so this list is intentionally empty but kept for future flat-check additions.
+          required_tech=()
+
+          missing=0
+
+          # Enforce src rules ONLY for src designs touched by PR
+          for d in "${!touched_src_design[@]}"; do
+            src_root="designs/src/$d"
+
+            # Require the directory itself
+            if [[ ! -d "$src_root" ]]; then
+              echo "::error file=designs/src::$src_root/ is required (touched by PR) but is missing."
+              missing=1
+              continue
+            fi
+
+            # Require files inside it
+            for req in "${required_src[@]}"; do
+              kind="${req%%:*}"
+              path="${req#*:}"
+
+              if [[ "$kind" == "file" ]]; then
+                if [[ ! -f "$src_root/$path" ]]; then
+                  echo "::error file=$src_root/$path::Missing required file: $src_root/$path"
+                  missing=1
+                fi
+              elif [[ "$kind" == "dir" ]]; then
+                if [[ ! -d "$src_root/$path" ]]; then
+                  echo "::error file=$src_root/$path::Missing required directory: $src_root/$path/"
+                  missing=1
+                fi
+              fi
+            done
+          done
+
+          # Enforce tech rules ONLY for tech/design trees touched by PR
+          for td in "${!touched_tech_design[@]}"; do
+            t="${td%%/*}"
+            d="${td#*/}"
+            tech_root="designs/$t/$d"
+
+            if [[ ! -d "$tech_root" ]]; then
+              echo "::error file=designs/$t::$tech_root/ is touched by PR but directory is missing."
+              missing=1
+              continue
+            fi
+
+            # Check required files recursively — each may live directly in <design>/ or in any subdir.
+            for req_file in config.mk constraint.sdc; do
+              if ! find "$tech_root" -name "$req_file" -type f -print -quit | grep -q .; then
+                echo "::error file=$tech_root::Missing required file: $req_file (expected anywhere under $tech_root/)"
+                missing=1
+              fi
+            done
+
+            for rel in "${required_tech[@]}"; do
+              if [[ ! -f "$tech_root/$rel" ]]; then
+                echo "::error file=$tech_root/$rel::Missing required file: $tech_root/$rel"
+                missing=1
+              fi
+            done
+          done
+
+          if (( missing )); then
+            echo "Validation failed."
+            exit 1
+          fi
+
+          echo "Validation passed."

.gitignore

@@ -9,6 +9,22 @@ objects
 .venv
 sv2v
 **/dev/liteeth_builds
+**/srecord/
+**/bazel
+**/sv2v*/
+**/python-*/
+**/systemc-*/
+**/perl-*/
+**/_build*/
+**/openssl*/
+**/_installed/
+**/_tarballs/
+**/*.log
+**/packages/
+**/generated/
 bazel-*
 MODULE.bazel.lock
+**/main/scala/
+**/target/
+**/sbt/
 .bazelrc.user

.gitmodules

@@ -1,21 +1,22 @@
 [submodule "OpenROAD-flow-scripts"]
 	path = OpenROAD-flow-scripts
 	url  = https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts.git
-[submodule "designs/src/lfsr_prbs_gen/dev/repo"]
-	path = designs/src/lfsr_prbs_gen/dev/repo
-	url = https://github.com/alexforencich/verilog-lfsr.git
 [submodule "designs/src/minimax/dev/repo"]
 	path = designs/src/minimax/dev/repo
 	url = https://github.com/gsmecher/minimax.git
-[submodule "designs/src/NyuziProcessor/dev/repo"]
-	path = designs/src/NyuziProcessor/dev/repo
-	url = https://github.com/jbush001/NyuziProcessor.git
 [submodule "designs/src/liteeth/dev/liteeth"]
 	path = designs/src/liteeth/dev/repo
 	url = https://github.com/enjoy-digital/liteeth.git
 [submodule "designs/src/cnn/dev/repo"]
 	path = designs/src/cnn/dev/repo
 	url = https://github.com/NNgen/nngen
+[submodule "designs/src/NVDLA/dev/repo"]
+	path = designs/src/NVDLA/dev/repo
+	url = https://github.com/nvdla/hw.git
+	branch = nv_small
+[submodule "designs/src/coralnpu/dev/repo"]
+	path = designs/src/coralnpu/dev/repo
+	url = https://github.com/google-coral/coralnpu.git
 [submodule "designs/src/gemmini/dev/repo"]
 	path = designs/src/gemmini/dev/repo
 	url = https://github.com/ucb-bar/gemmini.git
@@ -25,3 +26,15 @@
 [submodule "designs/src/sha3/dev/repo"]
 	path = designs/src/sha3/dev/repo
 	url = https://github.com/ucb-bar/sha3
+[submodule "FakeRAM"]
+	path = FakeRAM
+	url = https://github.com/VLSIDA/bsg_fakeram.git
+[submodule "designs/src/vortex/dev/repo"]
+	path = designs/src/vortex/dev/repo
+	url = https://github.com/vortexgpgpu/vortex.git
+[submodule "designs/src/lfsr_prbs_gen/dev/repo"]
+	path = designs/src/lfsr_prbs_gen/dev/repo
+	url = https://github.com/alexforencich/verilog-lfsr.git
+[submodule "designs/src/NyuziProcessor/dev/repo"]
+	path = designs/src/NyuziProcessor/dev/repo
+	url = https://github.com/jbush001/NyuziProcessor.git

Makefile

@@ -1,70 +1,35 @@
 ###            Comprehensive Design List (nangate45, sky130hd, asap7)            ###
-# 
-# DESIGN_CONFIG=./designs/nangate45/lfsr_prbs_gen/config.mk
+#
 # DESIGN_CONFIG=./designs/nangate45/minimax/config.mk
 # DESIGN_CONFIG=./designs/nangate45/NyuziProcessor/config.mk
 # 
-# DESIGN_CONFIG=./designs/sky130hd/lfsr_prbs_gen/config.mk
 # DESIGN_CONFIG=./designs/sky130hd/minimax/config.mk
 # 
+# DESIGN_CONFIG=./designs/asap7/sha3/config.mk
+# DESIGN_CONFIG=./designs/asap7/gemmini/config.mk
+# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_a/config.mk
+# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_c/config.mk
+# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_m/config.mk
+# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_o/config.mk
+# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_p/config.mk
+# DESIGN_CONFIG=./designs/asap7/coralnpu/config.mk
 # DESIGN_CONFIG=./designs/asap7/minimax/config.mk
-# DESIGN_CONFIG=./designs/asap7/lfsr_prbs_gen/config.mk
-# DESIGN_CONFIG=./designs/asap7/NyuziProcessor/config.mk
 # DESIGN_CONFIG=./designs/asap7/gemmini/config.mk
 # DESIGN_CONFIG=./designs/asap7/bp_processor/bp_quad/config.mk
 
-DESIGN_CONFIG ?= ./designs/nangate45/lfsr_prbs_gen/config.mk
+DESIGN_CONFIG ?= ./designs/asap7/lfsr_prbs_gen/config.mk
+
 -include OpenROAD-flow-scripts/flow/Makefile
-# Designs with RAM macros use FakeRAM (LEF generated for pins, no internal logic)
-# Check if calling "update-rtl" with an ORFS command or by itself.
-DEV_RUN_TAG?=x
-.PHONY: update-rtl
-ifeq ($(firstword $(MAKECMDGOALS)),update-rtl)
-DEV_RUN_TAG:=$(shell date +%s%N)$(shell bash -c "echo $$RANDOM")
-ifneq ($(lastword $(MAKECMDGOALS)),update-rtl)
-update-rtl: ;@:
-else
-$(info Starting update-rtl run)
-update-rtl: .dev-run-$(DESIGN_NAME)-$(DEV_RUN_TAG)
-endif
-endif
-export DEV_RUN_TAG
 
-.PHONY: do-dev-setup
-do-dev-setup:
+.PHONY: update_rtl
+update_rtl:
+	@$(MAKE) do-update
+
+.PHONY: do-update
+do-update:
 	git submodule init $(BENCH_DESIGN_HOME)/src/$(DEV_DESIGN_HOME)/repo
 	git submodule update $(BENCH_DESIGN_HOME)/src/$(DEV_DESIGN_HOME)/repo
-    # Check if a setup.sh script exists for the current design
 	@if [ -f "$(BENCH_DESIGN_HOME)/src/$(DEV_DESIGN_HOME)/setup.sh" ]; then \
 		bash $(BENCH_DESIGN_HOME)/src/$(DEV_DESIGN_HOME)/setup.sh; \
 	fi
-
-# .dev-suite-run flag is necessary because ORFS makefile unsets all vars for recursion
-.DELETE_ON_ERROR:
-.dev-run%:
-    # Change Design Nickname to avoid conflict between default and dev designs  
-	: > $@
-	$(MAKE) do-dev-setup 
-	@if [ ! -f "$(RESULTS_DIR)/1_synth.v" ]; then \
-		$(MAKE) finish; \
-	elif [ ! -f "$(RESULTS_DIR)/2_floorplan.odb" ]; then \
-		$(MAKE) do-floorplan do-place do-cts do-route do-finish; \
-	elif [ ! -f "$(RESULTS_DIR)/3_place.odb" ]; then \
-		$(MAKE) do-place do-cts do-route do-finish; \
-	elif [ ! -f "$(RESULTS_DIR)/4_cts.odb" ]; then \
-		$(MAKE) do-cts do-route do-finish; \
-	elif [ ! -f "$(RESULTS_DIR)/5_route.odb" ]; then \
-		$(MAKE) do-route do-finish; \
-	else \
-		$(MAKE) do-finish; \
-	fi
-	rm -f $@
-
-.PHONY: clean_design
-
-# DEV_SRC can be used to clean up any dev-dependent source files
-clean_design:
-	rm -rf $(DEV_SRC)
-
-clean_all: clean_design
-
+	@echo "Successfully updated Verilog RTL!"