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SYNtzulA #42

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49bf67b
SYNtzulA for sky130
paolopedroso Mar 27, 2026
b527255
fix license
paolopedroso Mar 31, 2026
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3 changes: 3 additions & 0 deletions .gitmodules
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Original file line number Diff line number Diff line change
Expand Up @@ -25,3 +25,6 @@
[submodule "designs/src/sha3/dev/repo"]
path = designs/src/sha3/dev/repo
url = https://github.com/ucb-bar/sha3
[submodule "designs/src/SYNtzulA/dev/repo"]
path = designs/src/SYNtzulA/dev/repo
url = https://github.com/EOLAB-2025/SYNtzulA.git
29 changes: 29 additions & 0 deletions designs/sky130hd/SYNtzulA/BUILD.bazel
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load("//:defs.bzl", "hightide_design")

filegroup(
name = "sram_lefs",
srcs = glob(["sram/lef/*.lef"])
)

filegroup(
name = "sram_libs",
srcs = glob(["sram/lib/*.lib"])
)

hightide_design(
name = "SYNtzulA",
top = "service_ihp_chip",
platform = "sky130hd",
verilog_files = ["//designs/src/SYNtzulA:rtl"],
sources = {
"SDC_FILE": [":constraint.sdc"],
"ADDITIONAL_LEFS": [":sram_lefs"],
"ADDITIONAL_LIBS": [":sram_libs"],
},
arguments = {
"DIE_AREA": "0 0 2290 2290",
"CORE_AREA": "40 40 2250 2250",
"PLACE_DENSITY": "0.60",
"HOLD_SLACK_MARGIN": "0.2",
},
)
14 changes: 14 additions & 0 deletions designs/sky130hd/SYNtzulA/config.mk
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export DESIGN_NAME = service_ihp_chip
export PLATFORM = sky130hd
export DESIGN_NICKNAME = SYNtzulA

-include $(BENCH_DESIGN_HOME)/src/$(DESIGN_NICKNAME)/verilog.mk

export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export DIE_AREA = 0 0 2290 2290
export CORE_AREA = 40 40 2250 2250

export PLACE_DENSITY = 0.60

export HOLD_SLACK_MARGIN = 0.2
21 changes: 21 additions & 0 deletions designs/sky130hd/SYNtzulA/constraint.sdc
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#################################################################### Design
current_design service_ihp_chip

#################################################################### Clock del sistema
set clk_name wb_clk
set clk_port_name wb_clk
set clk_period 8
set clk_port [get_ports $clk_port_name]
create_clock -name $clk_name -period $clk_period $clk_port

#################################################################### Clock del timer responsabile gating
set clk_name timer_clk
set clk_port_name timer_clk
set clk_period 100000
set clk_port [get_ports $clk_port_name]
create_clock -name $clk_name -period $clk_period $clk_port

set_max_fanout 8 [current_design]

set_false_path -from [get_ports wb_rst]
set_false_path -from [get_ports enb_debug]
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