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How to create an AIE baremetal platform for XCVE2302

Status: Open.

#43 In Xilinx/Vitis_Embedded_Platform_Source;

· micropuma opened on Jan 25, 2026

default path for PREBUILT common images

Status: Open.

#37 In Xilinx/Vitis_Embedded_Platform_Source;

· pooyaww opened on Mar 28, 2024

zcu102 dfx platform (22.1 ver.) long kernel latency

Status: Open.

#33 In Xilinx/Vitis_Embedded_Platform_Source;

· dj-park opened on Aug 13, 2023

flatform failed to build

Status: Open.

#32 In Xilinx/Vitis_Embedded_Platform_Source;

· nctran108 opened on Feb 11, 2023

Makefile:14: *** ERROR: 'BOOT_FILES_PATH' not set, please set this flag to path of boot files directory

Status: Open.

#30 In Xilinx/Vitis_Embedded_Platform_Source;

· Dinhding opened on Aug 12, 2022

Run 'impl_1' has not been launched. Unable to open

Status: Open.

#29 In Xilinx/Vitis_Embedded_Platform_Source;

· Zhang-Jia opened on Jul 30, 2021

ZCU102 DFX， the generated cpu clock is 1Mhz

Status: Open.

#19 In Xilinx/Vitis_Embedded_Platform_Source;

· luyufan498 opened on Sep 22, 2020

Vitis build error

Status: Open.

#18 In Xilinx/Vitis_Embedded_Platform_Source;

· thisisbaback opened on Sep 2, 2020

Running Vitis AI on Xilinx RF SoC

Status: Open.

#9 In Xilinx/Vitis_Embedded_Platform_Source;

· udara28 opened on May 27, 2020

rootfs generation failed : permission denied in do_rootfs

Status: Open.

#8 In Xilinx/Vitis_Embedded_Platform_Source;

· Morett07 opened on May 26, 2020

Erro for building zcu102_pl_ddr_stream platform

Status: Open.

#7 In Xilinx/Vitis_Embedded_Platform_Source;

· mbaharan opened on May 22, 2020

Vitis base platform for ZCU106 board

Status: Open.

#4 In Xilinx/Vitis_Embedded_Platform_Source;

· zohourih opened on Feb 28, 2020