L2-L2 inter-stamp memtile dtrace counters for VE2 baseline overlay - #100
L2-L2 inter-stamp memtile dtrace counters for VE2 baseline overlay#100predutta wants to merge 1 commit into
Conversation
There was a problem hiding this comment.
Pull request overview
Adds an optional VE2-specific extension to AIE dtrace “bandwidth” control-trace generation to also configure and sample a fixed set of memtile L2–L2 inter-stamp halo perf counters for the 24-column (1×6×4×4) baseline overlay, gated by AIE_dtrace_settings.l2_l2_transfer_metrics.
Changes:
- Extends VE2 bandwidth CT generation to append memtile L2–L2 perf counter resets/config writes plus additional
read_reg()samples and embedded metadata. - Introduces a fixed baseline mapping utility (
getL2L2CounterPoints) describing the 20 memtile counter points to configure/sample. - Adds metadata/config plumbing and improves CT-generation logging to reflect whether L2–L2 metrics are enabled.
Reviewed changes
Copilot reviewed 7 out of 7 changed files in this pull request and generated 2 comments.
Show a summary per file
| File | Description |
|---|---|
| profile/plugin/aie_dtrace/ve2/aie_dtrace_ve2.cpp | Updates CT-generation debug message to reflect “bandwidth” vs “bandwidth+L2-L2”. |
| profile/plugin/aie_dtrace/ve2/aie_dtrace_ct_writer.h | Extends CT writer API/state to support memtile L2–L2 counters and introduces memtile perf ctrl offsets/events. |
| profile/plugin/aie_dtrace/ve2/aie_dtrace_ct_writer.cpp | Appends memtile L2–L2 counter configuration, sampling, and metadata into the generated bandwidth CT. |
| profile/plugin/aie_dtrace/util/aie_dtrace_util.h | Adds L2–L2 baseline constants and the L2L2CounterPoint/API declaration. |
| profile/plugin/aie_dtrace/util/aie_dtrace_util.cpp | Implements the fixed 24-column baseline L2–L2 counter-point table. |
| profile/plugin/aie_dtrace/aie_dtrace_metadata.{h,cpp} | Adds l2_l2_transfer_metrics setting and exposes it via metadata. |
💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.
| auto tree = xrt_core::config::detail::get_ptree_value("AIE_dtrace_settings"); | ||
| if (auto val = tree.get_optional<bool>("config_one_partition")) | ||
| configOnePartition = *val; | ||
|
|
||
| l2L2TransferEnabled = xrt_core::config::get_aie_dtrace_settings_l2_l2_transfer_metrics(); | ||
|
|
| if (!allL2l2Counters.empty()) { | ||
| if (!metaGroups.empty()) | ||
| ctFile << ",\n"; | ||
| ctFile << "# \"l2_l2\": [\n"; |
|
@predutta I notice this feature is currently enabled via AIE_dtrace_settings.l2_l2_transfer_metrics. However, I recommend switching to AIE_dtrace_settings.tile_based_memory_tile_metrics instead. The reason is that if we add any new metrics under AIE_dtrace_settings.tile_based_memory_tile_metrics in the future, they will conflict with AIE_dtrace_settings.l2_l2_transfer_metrics since both consume the same underlying resources. CC: @jvillarre |
Adds optional L2-L2 inter-stamp memtile dtrace on the VE2 24-column (1×6×4×4) baseline by appending 20 perf counters on dst halo ports at memtile columns 1, 5, 9, 13, 17, and 21 (running + stall per path), merged into the existing bandwidth control-trace and sampled in the dtrace dump. Enable with AIE_dtrace_settings.l2_l2_transfer_metrics=true in xrt.ini alongside Debug.aie_dtrace=true. Memtile counters use row 1 (MEM_TILE_ROW_START) to match the overlay geometry and avoid invalid shim-row register accesses that previously caused FW exceptions.