This project presents the design and implementation of fundamental digital logic gates, a complete set of CMOS standard cells, and digital system designs using Cadence Virtuoso with the gpdk90 open-source PDK. Each cell and system has been designed from a transistor-level perspective, following a comprehensive VLSI design flow.
- Name: Ahasan Ullah Khalid
- Institution: Chittagong University of Engineering and Technology (CUET)
- Department: Electronics & Telecommunication Engineering (ETE)
- GitHub: github.com/aukhalid
- Website: aukhalid.vercel.app
This repository showcases the complete VLSI design flow for various digital circuits, starting from fundamental gates to more complex systems. The project meticulously follows these steps for each component:
- Transistor-level schematic design: Creating the logical representation of the circuit.
- DRC-clean layout implementation: Designing the physical layout of the circuit on silicon, ensuring it meets manufacturing rules.
- Symbol creation for hierarchical use: Generating a simplified graphical symbol for easy integration into larger designs.
- Circuit simulation in ADE L: Running pre-layout and post-layout simulations to verify functionality.
- Verification against theoretical truth tables: Confirming that the circuit's behavior matches its intended logical function.
- Cadence Virtuoso: The primary EDA tool used for schematic capture, layout design, and simulation.
- gpdk90 Open-Source PDK: The process design kit (PDK) providing the technology-specific design rules and device models.
- CMOS VLSI Design Principles: The theoretical foundation for all circuit implementations.
The project is divided into two major sections:
This section includes the foundational building blocks of digital logic.
- Inverter (NOT Gate)
- 2-input NAND Gate (NAND2X1)
- 2-input AND Gate (AND2X1)
- 2-input NOR Gate (NOR2X1)
- 2-input OR Gate (OR2X1)
- M1_NWELL (PMOS well connection)
- M1_PSUB (NMOS substrate connection)
This section demonstrates the use of standard cells to create more complex digital systems using a hierarchical design approach.
- Half Adder (HA)
- Full Adder (FA)
- 1 x 2 De-Multiplexer
- 1 x 8 De-Multiplexer
Each standard cell entry is presented with the following format:
- Objective: The goal of the design.
- Description: A brief overview of the circuit's function and implementation.
- Design Steps: A step-by-step guide to the design process.
- Schematic Diagram: The transistor-level schematic.
- Layout: The physical representation of the circuit.
- Symbol: The hierarchical symbol.
- Simulation & Verification: The simulation results and a truth table.
Objective: To create the simplest form of a logic gate that outputs the complement of the input signal.
Description: The CMOS inverter is composed of a PMOS and an NMOS transistor. The PMOS transistor pulls the output up to VDD when the input is low, and the NMOS transistor pulls the output down to GND when the input is high.
| A | Y |
|---|---|
| 0 | 1 |
| 1 | 0 |
Design Steps:
- Schematic Design: Place a PMOS (source to VDD) and an NMOS (source to GND). Connect their drains to the output
Yand their gates to the inputA. - Layout Design: Draw diffusion layers for PMOS (in N-well) and NMOS (on P-substrate). Route metal layers for VDD, GND, input
A, and outputY. - Symbol Creation: Generate a standard inverter symbol with input
Aand outputY. - Simulation: Run a transient analysis with a pulsed input and verify the inverted output waveform.
Schematic Diagram:
Layout:
Symbol:
Simulation & Verification:
The simulation confirmed that when the input A is low, the output Y is high, and vice versa.
Objective: To design, lay out, and verify a 2-input CMOS NAND gate.
Description: A 2-input CMOS NAND gate outputs logic '0' only when both inputs are '1'. It uses two parallel PMOS transistors in the pull-up network (PUN) and two series NMOS transistors in the pull-down network (PDN).
Truth Table:
| A | B | Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Design Steps:
- Schematic (Transistor-Level): Instantiate two PMOS in parallel between VDD and
Y. Instantiate two NMOS in series betweenYand GND. - Layout: Arrange the transistors, route connections, and add well/substrate taps. Ensure DRC compliance.
- LVS & Extraction: Run LVS to verify the layout matches the schematic.
- Symbol: Create a symbol with inputs
A,B, and outputY.
Schematic Diagram:
Layout:
Symbol:
Simulation & Verification:
Transient analysis confirmed that the output Y is low only when both inputs A and B are high.
Objective: To design and verify a 2-input AND gate using a hierarchical approach by cascading a NAND gate and an Inverter.
Description: The Boolean expression for an AND gate is
Truth Table:
| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Design Steps:
- Hierarchical Schematic: Instantiate the
NAND2X1andInverterstandard cells. - Schematic Capture: Connect the inputs
AandBto theNAND2X1. Connect the output of theNAND2X1to the input of theInverter. TheInverter's output is the final outputY. - Layout: Place the
NAND2X1andInverterlayouts and route the interconnections. - Simulation: Run a transient analysis to verify the output
Yis high only when both inputsAandBare high.
Schematic Diagram:
Layout:
Symbol:
Simulation & Verification:
The simulation confirmed that the circuit performs the AND function correctly.
Objective: To design and verify a 2-input NOR gate from a transistor-level perspective.
Description: A NOR gate outputs a low signal if any of its inputs are high. It is implemented with two series PMOS transistors and two parallel NMOS transistors. The Boolean expression is
Truth Table:
| A | B | Y |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
Design Steps:
- Schematic Design: Use two series PMOS transistors for the pull-up network and two parallel NMOS transistors for the pull-down network.
- Layout Generation: Place the transistors and route the connections to form the series and parallel networks.
- DRC/LVS: Verify the layout against the design rules and schematic.
- Simulation: Perform a transient analysis to check all four input combinations.
Schematic Diagram:
Symbol:
Layout:
Simulation & Verification:
The simulation results matched the NOR gate's truth table, validating the design.
Objective: To design a 2-input OR gate using a hierarchical approach by cascading a NOR gate and an Inverter.
Description: An OR gate outputs a high signal if any of its inputs are high. The expression
Truth Table:
| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
Design Steps:
- Hierarchical Schematic: Instantiate the
NOR2X1andInverterstandard cells. - Schematic Capture: Connect the inputs
AandBto theNOR2X1. Connect the output of theNOR2X1to the input of theInverter. TheInverter's output isY. - Layout: Arrange the layouts of the two cells and route the connections.
- Simulation: Run a transient analysis and confirm the output
Ymatches the OR gate's truth table.
Schematic Diagram:
Layout:
Symbol:
Simulation & Verification:
The simulation successfully validated the OR gate's operation.
Objective: To understand the purpose and physical representation of the N-Well layer.
Description: The M1_NWELL layer represents the N-Well, a region of the silicon substrate doped with n-type impurities. It provides the necessary environment to house PMOS transistors, whose body must be tied to the highest potential (VDD).
Layout:
In the layout, this layer encloses all PMOS transistors and is connected to VDD via a P-type tap.
Objective: To understand the purpose and physical representation of the P-Substrate layer.
Description: The M1_PSUB layer represents the connection to the P-Substrate, the bulk silicon wafer. It provides a stable body potential for NMOS transistors, which are built directly on the substrate. This layer must be connected to the lowest potential (GND) to prevent latch-up.
Layout:
In the layout, this layer is represented by a specific contact that ties a metal layer to the P-Substrate, typically connected to GND via N-type taps.
Each entry in this section is also presented with the same format as the standard cells, demonstrating the hierarchical design approach. And the following format:
- Objective: The goal of the design.
- Description: A brief overview of the circuit's function and implementation.
- Design Steps: A step-by-step guide to the design process.
- Schematic Diagram: The transistor-level schematic.
- Layout: The physical representation of the circuit.
- Symbol: The hierarchical symbol.
- Simulation & Verification: The simulation results and a truth table.
Objective: To design a 1-bit half adder circuit using only 2-input NAND gates, demonstrating the universality of the NAND gate.
Description: A half adder adds two single bits A and B to produce a Sum and a Carry. The logic is Sum = A XOR B and Carry = A AND B. These functions are implemented using a network of NAND gates.
Truth Table:
| A | B | Sum | Carry |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Design Steps:
- Schematic Design: Build the circuit by instantiating
NAND2X1cells to form the XOR and AND logic functions. - Layout Generation: Place the NAND gate layouts and route the connections.
- Simulation: Run a transient analysis to verify the
SumandCarryoutputs match the truth table.
Schematic Diagram:
Layout:
Symbol:
Simulation & Verification:
The simulation confirmed that the circuit correctly performs 1-bit binary addition.
Objective: To design and verify a 1-bit full adder circuit using a hierarchical approach, building it from NAND-based half adders and OR gates.
Description: A full adder adds three single-bit numbers (A, B, Cin) to produce a Sum and a Cout. The circuit is built by cascading two half adders and an OR gate.
Truth Table:
| A | B | Cin | Y (Sum) | Cout |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Design Steps:
- Hierarchical Schematic: Instantiate two NAND-based half adders and an OR gate.
- Schematic Capture: Connect the inputs
A,B, andCinto form the full adder circuit. - Layout Generation: Place the sub-blocks and route the connections.
- Simulation: Run a transient analysis to test all eight input combinations.
Schematic Diagram:
Layout:
Symbol:
Simulation & Verification:
The simulation results validated that the full adder correctly performed 1-bit binary addition with a carry-in.
Objective: To design a 1x2 demultiplexer (DEMUX) circuit using only 2-input NAND gates.
Description: A 1x2 DEMUX routes a single data input (D) to one of two outputs (Y0, Y1) based on the value of a select line (S). The logic is
Truth Table:
| S | D | Y0 | Y1 |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 |
Design Steps:
- Schematic Design: Build the AND gate logic using NAND gates to realize the output expressions.
- Layout Generation: Place the NAND gate layouts and route the connections.
- Simulation: Verify that the data input is correctly routed to the selected output.
Schematic Diagram:
Layout:
Symbol:
Simulation & Verification:
The simulation confirmed that the circuit performed the demultiplexing operation as intended.
Objective:
The objective is to design, implement, and verify a 1-to-8 demultiplexer (DEMUX) circuit using a hierarchical approach, building it entirely from pre-existing 1x2 demultiplexer standard cells.
Description:
A 1x8 demultiplexer is a combinational logic circuit with one data input (
The circuit is built by cascading 1x2 demultiplexer cells in a tree structure. A 1x8 DEMUX requires a total of seven 1x2 DEMUX units arranged in three stages:
-
Stage 1: One 1x2 DEMUX with data input
$D$ and select line$S_2$ . -
Stage 2: Two 1x2 DEMUX units, with their inputs connected to the outputs of the Stage 1 DEMUX. The select line for these is
$S_1$ . -
Stage 3: Four 1x2 DEMUX units, with their inputs connected to the outputs of the Stage 2 DEMUXs. The select line for these is
$S_0$ .
Design Steps:
-
Hierarchical Schematic Design: The design is created by instantiating and connecting seven of the pre-built
DEMUX1X2cells. The top-level schematic will show these cells in a clear, tree-like arrangement. -
Schematic Capture: The data input
$D$ is connected to the first stageDEMUX1X2's data pin, and the select line$S_2$ is connected to its select pin. The two outputs of this first stage are routed to the data inputs of the twoDEMUX1X2cells in the second stage. The select line for these two is$S_1$ . The four outputs from the second stage feed the data inputs of the fourDEMUX1X2cells in the final, third stage, which are controlled by select line$S_0$ . -
Layout: The layout is created by placing the seven
DEMUX1X2layouts. The cells are arranged to follow the hierarchical tree structure for clean and efficient routing. The select lines ($S_0$ ,$S_1$ ,$S_2$ ) and the data input ($D$ ) are routed to minimize wire length and parasitic effects. The total transistor count is 35. -
DRC/LVS: Perform a Design Rule Check (DRC) to ensure the layout adheres to all manufacturing rules. Execute a Layout Versus Schematic (LVS) to verify that the physical layout accurately represents the hierarchical schematic.
-
Simulation Setup: In the Cadence ADE L environment, a transient analysis is configured. Pulsed voltage sources are applied to the data input
$D$ and the three select lines$S_0$ ,$S_1$ , and$S_2$ . All 8 combinations of the select lines are tested to ensure full functionality. -
Simulation & Verification: The simulation is run, and the output waveforms for
$Y_0$ through$Y_7$ are observed. The output on the selected line should mirror the input data, while all other outputs remain low. This is compared against the demultiplexer's truth table.
Schematic Diagram:
The schematic diagram clearly shows the cascading structure of the seven 1x2 DEMUX cells, with the select lines controlling each stage of the tree.
Layout:
The layout visually represents the physical placement of the DEMUX1X2 cells and the careful routing of signal and power lines to achieve a compact and functional design.
Symbol:
The symbol is a top-level representation of the 1x8 demultiplexer, showing its single data input, three select lines, and eight outputs.
Simulation & Verification:
The simulation plot below shows the waveforms for the inputs and outputs, confirming that the circuit performs the correct demultiplexing function. The output goes high only on the line corresponding to the binary value of the select lines. For example, when
| 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
The simulation confirms that the designed circuit successfully routes the data input to the selected output, validating its functionality for all eight possible input combinations.
