ml-hpi

Multi-Language Hierarchical Programming Interface

ml-hpi defines a declarative, language-neutral specification for verification APIs. From a single source — authored in YAML/JSON or derived from an existing SystemVerilog interface class — ml-hpi generates correct, idiomatic bindings for SystemVerilog, C++, Python, C, and PSS simultaneously.

Motivation

SoC verification requires the same test intent to run across block-level simulation, subsystem integration, full-chip simulation, emulation, and silicon bring-up. ml-hpi addresses this on two levels. First, interface abstraction decouples test logic from any specific testbench hierarchy so the same test runs unchanged from block to SoC — even in a pure-SystemVerilog environment. Second, a shared semantic model automates the otherwise hand-written glue needed when multiple languages are in play: C++, Python, and PSS bindings are generated from the same spec, never maintained by hand.

Key features:

• Hierarchical context — interfaces are typed objects with field and array sub-interface members; tests navigate chip.uarts_at(1).send(ch) naturally
• Blocking semantics — blocking, target, and solve attributes per method; generators emit task in SV, async def in Python, etc. automatically
• Derive from SV — extract the IDL from an existing interface class hierarchy; C++, Python, C, and PSS bindings are generated with no manual work
• PSS integration — the same spec generates PSS component and function import declarations, bridging portable stimulus to existing UVM/C++ implementations

Documentation

https://fvutils.github.io/ml-hpi

License

Apache 2.0 — see LICENSE.