iverilog-even-sequence-generator

Design and implementation of an even number(0->2->4->6->8) sequence generator using the simulation and synthesis tool iverilog

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
Algorithm.pdf		Algorithm.pdf
Circuit Diagram.png		Circuit Diagram.png
README.md		README.md
main.v		main.v
main_tb.v		main_tb.v

Provide feedback