Adds support for aliases. #4

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martinhansdk wants to merge 1 commit into ldoolitt:master from martinhansdk:master

martinhansdk commented Oct 2, 2017

Maps the VHDL alias keyword to the Verilog alias keyword.


          Adds support for aliases.

d9096db

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ldoolitt commented Nov 29, 2017

I can believe this addresses your use case. Do you have an example Verilog module that uses alias?
I can't get it to go through iverilog.

petterreinholdtsen commented Jul 16, 2025

Note, the code base mentioned in #26 also uses aliases. A link to download it is available there.

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